Co-design of wafer level thin film package assembly

An increasing number of semiconductor companies have research programs related to MEMS products. This can be explained by the wide variety of application areas for MEMS, some mechanical MEMS examples are: filters [1], oscillators [2,3], pressure sensors [4], particle detection [5], thermometers [6] and gyroscopes [7]. Many mechanical MEMS operate in vacuum and sealing of the cavity can be obtained by using a wafer level thin film package or zero level package. Such a package consists of a thin film cap, which is released by etching away a sacrificial layer, and a sealing structure. The main advantage of this method towards others such as local assembly is that all caps can be made in one time and the small scale of the sealing. To fit a MEMS into a small (plastic) package the die needs to be processed in several steps. Examples are: wafer thinning and dicing. In earlier research it was shown that wafer thinning is one of the potentially more hazardous assembly processes due to the large mechanical forces exerted on the wafer [8]. This paper presents an extensive DOE to assess the performance of Wafer Level Thin Film Packages (WLTFP¿s) under assembly processes . The influences of the wafer thinning process on a large variety of WLTFP¿s are quantified. A selection of relevant samples is also tested in other key assembly steps like dicing, die-attach and moulding.