Compact delay modeling of latch-based threshold logic gates

MD Padure, SD Cotofana, C Dan, S Vassiliadis, M Bodea

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

Original languageUndefined/Unknown
Title of host publicationCAS 2002 Proceedings, Volume 2
Place of PublicationPiscataway, NJ, USA
PublisherIEEE Society
Pages317-320
Number of pages4
ISBN (Print)0-7803-7440-1
Publication statusPublished - 2002
Event2002 International semiconductor conference, 25th edition - Piscataway, NJ, USA
Duration: 8 Oct 200212 Oct 2002

Publication series

Name
PublisherIEEE
Name
Volume2

Conference

Conference2002 International semiconductor conference, 25th edition
Period8/10/0212/10/02

Keywords

  • Elektrotechniek
  • Techniek
  • conference contrib. refereed
  • Conf.proc. > 3 pag

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