Computation-in-memory based parallel adder

HA Du Nguyen; L Xie; M Taouil; R Nane; S Hamdioui; K Bertels

doi:10.1109/NANOARCH.2015.7180587

Computation-in-memory based parallel adder

HA Du Nguyen, L Xie, M Taouil, R Nane, S Hamdioui, K Bertels

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

21 Citations (Scopus)

Original language	English
Title of host publication	Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH
Editors	CA Moritz, M Rahman
Place of Publication	Piscataway
Publisher	IEEE Society
Pages	57-62
Number of pages	6
ISBN (Print)	978-1-4673-7849-9
DOIs	https://doi.org/10.1109/NANOARCH.2015.7180587
Publication status	Published - 2015
Event	NANOARCH 2015, Boston, USA - Duration: 8 Jul 2015 → 10 Jul 2015

Publication series

Name
Publisher	IEEE

Conference

Conference	NANOARCH 2015, Boston, USA
Period	8/07/15 → 10/07/15

Bibliographical note

harvest

Access to Document

10.1109/NANOARCH.2015.7180587

Cite this

@inproceedings{a0f60c06fb794012914a414cc555022e,

title = "Computation-in-memory based parallel adder",

author = "{Du Nguyen}, HA and L Xie and M Taouil and R Nane and S Hamdioui and K Bertels",

note = "harvest; NANOARCH 2015, Boston, USA ; Conference date: 08-07-2015 Through 10-07-2015",

year = "2015",

doi = "10.1109/NANOARCH.2015.7180587",

language = "English",

isbn = "978-1-4673-7849-9",

publisher = "IEEE Society",

pages = "57--62",

editor = "CA Moritz and M Rahman",

booktitle = "Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH",

}

Computation-in-memory based parallel adder. / Du Nguyen, HA; Xie, L; Taouil, M et al.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH. ed. / CA Moritz; M Rahman. Piscataway: IEEE Society, 2015. p. 57-62.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Computation-in-memory based parallel adder

AU - Du Nguyen, HA

AU - Xie, L

AU - Taouil, M

AU - Nane, R

AU - Hamdioui, S

AU - Bertels, K

N1 - harvest

PY - 2015

Y1 - 2015

U2 - 10.1109/NANOARCH.2015.7180587

DO - 10.1109/NANOARCH.2015.7180587

M3 - Conference contribution

SN - 978-1-4673-7849-9

SP - 57

EP - 62

BT - Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH

A2 - Moritz, CA

A2 - Rahman, M

PB - IEEE Society

CY - Piscataway

T2 - NANOARCH 2015, Boston, USA

Y2 - 8 July 2015 through 10 July 2015

ER -