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Context aware slope based transistor-level aging model. / Cucu Laurenciu, N; Cotofana, SD.

In: Microelectronics Reliability, Vol. 52, No. 9-10, 2012, p. 1-6.

Research output: Contribution to journalArticleScientificpeer-review

Harvard

Cucu Laurenciu, N & Cotofana, SD 2012, 'Context aware slope based transistor-level aging model' Microelectronics Reliability, vol. 52, no. 9-10, pp. 1-6.

APA

Vancouver

Author

Cucu Laurenciu, N ; Cotofana, SD. / Context aware slope based transistor-level aging model. In: Microelectronics Reliability. 2012 ; Vol. 52, No. 9-10. pp. 1-6.

BibTeX

@article{2b1695adb7af466a9bcdd7114d1e65f6,
title = "Context aware slope based transistor-level aging model",
author = "{Cucu Laurenciu}, N and SD Cotofana",
year = "2012",
language = "English",
volume = "52",
pages = "1--6",
journal = "Microelectronics Reliability",
issn = "0026-2714",
publisher = "Elsevier",
number = "9-10",

}

RIS

TY - JOUR

T1 - Context aware slope based transistor-level aging model

AU - Cucu Laurenciu, N

AU - Cotofana, SD

PY - 2012

Y1 - 2012

UR - http://ce-publications.et.tudelft.nl/publications/1318_context_aware_slope_based_transistorlevel_aging_model.pdf

M3 - Article

VL - 52

SP - 1

EP - 6

JO - Microelectronics Reliability

T2 - Microelectronics Reliability

JF - Microelectronics Reliability

SN - 0026-2714

IS - 9-10

ER -

ID: 3146246