Abstract
Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS.
Original language | English |
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Title of host publication | 2016 IEEE International Electron Devices Meeting, IEDM 2016 |
Place of Publication | Piscataway, NJ |
Publisher | IEEE |
Pages | 343-346 |
Number of pages | 4 |
ISBN (Electronic) | 978-1-5090-3902-9 |
DOIs | |
Publication status | Published - 2017 |
Event | IEDM 2016: 62nd IEEE International Electron Devices Meeting - San Francisco, CA, United States Duration: 3 Dec 2016 → 7 Dec 2016 Conference number: 62 http://ieee-iedm.org/ |
Conference
Conference | IEDM 2016 |
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Abbreviated title | IEDM |
Country/Territory | United States |
City | San Francisco, CA |
Period | 3/12/16 → 7/12/16 |
Internet address |
Bibliographical note
13.5Keywords
- Quantum dots
- Quantum computing
- Multiplexing
- Field programmable gate arrays
- Fault tolerance
- Fault tolerant system
- Computers