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Degradation analysis of high performance 14nm FinFET SRAM. / Kraak, D.; Agbo, I.; Taouil, M.; Hamdioui, S.; Weckx, P.; Cosemans, S.; Catthoor, F.

2018 Design, Automation Test in Europe Conference Exhibition (DATE). 2018. p. 201-206.

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Kraak, D, Agbo, I, Taouil, M, Hamdioui, S, Weckx, P, Cosemans, S & Catthoor, F 2018, Degradation analysis of high performance 14nm FinFET SRAM. in 2018 Design, Automation Test in Europe Conference Exhibition (DATE). pp. 201-206. https://doi.org/10.23919/DATE.2018.8342003

APA

Kraak, D., Agbo, I., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S., & Catthoor, F. (2018). Degradation analysis of high performance 14nm FinFET SRAM. In 2018 Design, Automation Test in Europe Conference Exhibition (DATE) (pp. 201-206) https://doi.org/10.23919/DATE.2018.8342003

Vancouver

Kraak D, Agbo I, Taouil M, Hamdioui S, Weckx P, Cosemans S et al. Degradation analysis of high performance 14nm FinFET SRAM. In 2018 Design, Automation Test in Europe Conference Exhibition (DATE). 2018. p. 201-206 https://doi.org/10.23919/DATE.2018.8342003

Author

Kraak, D. ; Agbo, I. ; Taouil, M. ; Hamdioui, S. ; Weckx, P. ; Cosemans, S. ; Catthoor, F. / Degradation analysis of high performance 14nm FinFET SRAM. 2018 Design, Automation Test in Europe Conference Exhibition (DATE). 2018. pp. 201-206

BibTeX

@inproceedings{e796de603f89447f94943141a7aa6767,
title = "Degradation analysis of high performance 14nm FinFET SRAM",
abstract = "Memory designs usually add design margins to compensate for chip aging; this may lead to yield and performance loss (in case of overestimation) or reduced reliability (in case of underestimation). This paper analyzes the impact of aging on cutting edge high performance 14nm FinFET SRAM using a calibrated aging model; it does not only analyze the impact of the SRAM's components individually, as it is the case in prior work, but it also investigates the contribution of the interaction of these components while considering different workloads; both the overall metric of the memory (i.e., the access time) as well as metrics of individual components (e.g., sensing delay for the sense amplifier) are examined. The results show that it is crucial to consider not only the aging of all individual components, but also their interaction in order to provide accurate prediction of aging effects; considering only aging of single/individual components leads to either too optimistic or pessimistic results. For example, using our approach (which includes the components interaction) results approximately in 9.1{\%} degradation of memory access time (for three years of aging), while using the traditional approach (based on adding the impact of individual components) results in 7.3{\%} increase only; a relative difference of 25{\%}, for which the timing and the address decoder components are the main contributors. With respect to individual components, the sense amplifier is the most fragile one (e.g., its offset voltage spec. degrades up to 58{\%}).",
keywords = "performance evaluation, SRAM chips, SRAM components, degradation analysis, high performance 14nm FinFET SRAM, address decoder components, memory access time, components interaction, aging effects, sense amplifier, calibrated aging model, performance loss, chip aging, design margins, memory designs, Decoding, Aging, Sensors, Delays, Degradation, Reliability, aging, SRAM, FinFET",
author = "D. Kraak and I. Agbo and M. Taouil and S. Hamdioui and P. Weckx and S. Cosemans and F. Catthoor",
year = "2018",
month = "3",
day = "1",
doi = "10.23919/DATE.2018.8342003",
language = "Undefined/Unknown",
pages = "201--206",
booktitle = "2018 Design, Automation Test in Europe Conference Exhibition (DATE)",

}

RIS

TY - GEN

T1 - Degradation analysis of high performance 14nm FinFET SRAM

AU - Kraak, D.

AU - Agbo, I.

AU - Taouil, M.

AU - Hamdioui, S.

AU - Weckx, P.

AU - Cosemans, S.

AU - Catthoor, F.

PY - 2018/3/1

Y1 - 2018/3/1

N2 - Memory designs usually add design margins to compensate for chip aging; this may lead to yield and performance loss (in case of overestimation) or reduced reliability (in case of underestimation). This paper analyzes the impact of aging on cutting edge high performance 14nm FinFET SRAM using a calibrated aging model; it does not only analyze the impact of the SRAM's components individually, as it is the case in prior work, but it also investigates the contribution of the interaction of these components while considering different workloads; both the overall metric of the memory (i.e., the access time) as well as metrics of individual components (e.g., sensing delay for the sense amplifier) are examined. The results show that it is crucial to consider not only the aging of all individual components, but also their interaction in order to provide accurate prediction of aging effects; considering only aging of single/individual components leads to either too optimistic or pessimistic results. For example, using our approach (which includes the components interaction) results approximately in 9.1% degradation of memory access time (for three years of aging), while using the traditional approach (based on adding the impact of individual components) results in 7.3% increase only; a relative difference of 25%, for which the timing and the address decoder components are the main contributors. With respect to individual components, the sense amplifier is the most fragile one (e.g., its offset voltage spec. degrades up to 58%).

AB - Memory designs usually add design margins to compensate for chip aging; this may lead to yield and performance loss (in case of overestimation) or reduced reliability (in case of underestimation). This paper analyzes the impact of aging on cutting edge high performance 14nm FinFET SRAM using a calibrated aging model; it does not only analyze the impact of the SRAM's components individually, as it is the case in prior work, but it also investigates the contribution of the interaction of these components while considering different workloads; both the overall metric of the memory (i.e., the access time) as well as metrics of individual components (e.g., sensing delay for the sense amplifier) are examined. The results show that it is crucial to consider not only the aging of all individual components, but also their interaction in order to provide accurate prediction of aging effects; considering only aging of single/individual components leads to either too optimistic or pessimistic results. For example, using our approach (which includes the components interaction) results approximately in 9.1% degradation of memory access time (for three years of aging), while using the traditional approach (based on adding the impact of individual components) results in 7.3% increase only; a relative difference of 25%, for which the timing and the address decoder components are the main contributors. With respect to individual components, the sense amplifier is the most fragile one (e.g., its offset voltage spec. degrades up to 58%).

KW - performance evaluation

KW - SRAM chips

KW - SRAM components

KW - degradation analysis

KW - high performance 14nm FinFET SRAM

KW - address decoder components

KW - memory access time

KW - components interaction

KW - aging effects

KW - sense amplifier

KW - calibrated aging model

KW - performance loss

KW - chip aging

KW - design margins

KW - memory designs

KW - Decoding

KW - Aging

KW - Sensors

KW - Delays

KW - Degradation

KW - Reliability

KW - aging

KW - SRAM

KW - FinFET

U2 - 10.23919/DATE.2018.8342003

DO - 10.23919/DATE.2018.8342003

M3 - Conference contribution

SP - 201

EP - 206

BT - 2018 Design, Automation Test in Europe Conference Exhibition (DATE)

ER -

ID: 47878761