DOI

Device aging is an important concern in nanoscale designs. Due to aging the electrical behavior of transistors embedded in an integrated circuit deviates from original intended one. This leads to performance degradation in the underlying device, and the ultimate device failure. This effect is exacerbated in emerging technologies. To be able to tailor effective aging mitigation schemes and improve the reliability of devices realized in cutting edge technologies, there is a need to accurately study the effect of aging in high performance industrial applications. According, this paper targets a high performance SRAM memory realized in 14nm FinFET technology and depicts how aging degrades the individual components of this memory as well as the interaction between them. Aging mitigation is critical not only from device reliability point of view but also regarding device security perspectives. It is essential to assure the security of the sensitive tasks performed by the security-sensitive circuits and to guarantee the security of information stored within these devices in the presence of aging. Accordingly in this paper, we also focus on aging-related security concerns and present the cases in which aging need to considered to preserve security.
Original languageUndefined/Unknown
Title of host publication2018 IEEE 23rd European Test Symposium (ETS)
Pages1-10
Number of pages10
DOIs
Publication statusPublished - 1 May 2018

    Research areas

  • ageing, failure analysis, MOSFET, semiconductor device reliability, SRAM chips, device aging, edge technologies, high performance SRAM memory, security-sensitive circuits, aging-related security concerns, FinFET technology, size 14.0 nm, Degradation, Aging, Delays, Reliability, Decoding, Transistors

ID: 47878715