Abstract
Hard-to-detect faults such as weak and random faults in FinFET SRAMs represent an important challenge for manufacturing testing in scaled technologies, as they may lead to test escapes. This paper proposes a Design-for-Testability (DFT) scheme able to detect such faults by monitoring the bitline swing of FinFET memories. Using only five operations per cell, we are able to detect defects that cause deterministic, random, and weak faults. Compared to the state of the art, this leads to an improved detection capability at reduced area overhead.
Original language | English |
---|---|
Title of host publication | Proceedings - 2019 IEEE European Test Symposium, ETS 2019 |
Subtitle of host publication | Proceedings |
Publisher | IEEE |
Pages | 1-2 |
Number of pages | 2 |
Volume | 2019-May |
ISBN (Electronic) | 978-1-7281-1173-5 |
ISBN (Print) | 978-1-7281-1174-2 |
DOIs | |
Publication status | Published - 2019 |
Event | 24th IEEE European Test Symposium 2019 - Baden-Baden, Germany Duration: 27 May 2019 → 31 May 2019 Conference number: 24th http://www.testgroup.polito.it/ets19 |
Conference
Conference | 24th IEEE European Test Symposium 2019 |
---|---|
Abbreviated title | ETS |
Country/Territory | Germany |
City | Baden-Baden |
Period | 27/05/19 → 31/05/19 |
Internet address |
Bibliographical note
Accepted author manuscriptKeywords
- Hard-to-Detect Faults
- DFT
- SRAM
- FinFET