Spin-transfer-torque magnetic RAM (STT-MRAM) is one of the most promising emerging memory technologies. As various manufacturing vendors make significant efforts to push it to the market, appropriate STT-MRAM testing is of
great importance. In this paper, we demonstrate that conventional STT-MRAM defect modeling, which is based on linear resistors, is too pessimistic in representing the real nature of physical defects. It may result in incorrect fault models, which in turn can lead to low-quality test solutions. In addition, we propose a generic defect modeling methodology which captures the nonlinear
behavior of STT-MRAM defects accurately; a defect is modeled by adjusting the affected STT-MRAM technology parameters. The methodology is illustrated by two examples, namely a pinhole defect and a sidewall redeposition defect,
which are simulated for accurate fault modeling. In case of a pinhole defect, the STT-MRAM suffers from a fast transition between magnetic tunnel junction (MTJ) states with increased write current, making the MTJ more vulnerable to breakdown. However, with the conventional linear resistor as defect model
the memory shows a slow transition or even a transition failure. Similarly, a sidewall redeposition defect causes a fast transition without current elevation, which is not observed when using the conventional approach.
Original languageEnglish
Title of host publicationInternational Test Conference
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages1-10
Number of pages10
Publication statusAccepted/In press - 2019
EventITC 2018: International Test Conference - Phoenix Convention Center, Phoenix, AZ, United States
Duration: 28 Oct 20182 Nov 2018
http://www.itctestweek.org/

Conference

ConferenceITC 2018
CountryUnited States
CityPhoenix, AZ
Period28/10/182/11/18
OtherCo-located with ISTFA 2018
Internet address

ID: 47858565