Energy effective 3D stacked hybrid NEMFET-CMOS caches

M Lefter; M Enachescu; GR Voicu; SD Cotofana

doi:10.1109/NANOARCH.2014.6880506

Energy effective 3D stacked hybrid NEMFET-CMOS caches

M Lefter, M Enachescu, GR Voicu, SD Cotofana

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

5 Citations (Scopus)

Original language	English
Title of host publication	Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures
Editors	JO Klein, CA Moritz
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE Society
Pages	151-156
Number of pages	6
ISBN (Print)	978-1-4799-6383-6
DOIs	https://doi.org/10.1109/NANOARCH.2014.6880506
Publication status	Published - 2014
Event	NANOARCH 2014, Paris, France - Piscataway, NJ, USA Duration: 8 Jul 2014 → 10 Jul 2014

Publication series

Name
Publisher	IEEE

Conference

Conference	NANOARCH 2014, Paris, France
Period	8/07/14 → 10/07/14

Access to Document

10.1109/NANOARCH.2014.6880506

Cite this

@inproceedings{acea3cfa83be422a8c10f160a804b252,

title = "Energy effective 3D stacked hybrid NEMFET-CMOS caches",

author = "M Lefter and M Enachescu and GR Voicu and SD Cotofana",

year = "2014",

doi = "10.1109/NANOARCH.2014.6880506",

language = "English",

isbn = "978-1-4799-6383-6",

publisher = "IEEE Society",

pages = "151--156",

editor = "JO Klein and CA Moritz",

booktitle = "Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures",

note = "NANOARCH 2014, Paris, France ; Conference date: 08-07-2014 Through 10-07-2014",

}

Energy effective 3D stacked hybrid NEMFET-CMOS caches. / Lefter, M; Enachescu, M; Voicu, GR et al.
Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures. ed. / JO Klein; CA Moritz. Piscataway, NJ, USA: IEEE Society, 2014. p. 151-156.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Energy effective 3D stacked hybrid NEMFET-CMOS caches

AU - Lefter, M

AU - Enachescu, M

AU - Voicu, GR

AU - Cotofana, SD

PY - 2014

Y1 - 2014

U2 - 10.1109/NANOARCH.2014.6880506

DO - 10.1109/NANOARCH.2014.6880506

M3 - Conference contribution

SN - 978-1-4799-6383-6

SP - 151

EP - 156

BT - Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures

A2 - Klein, JO

A2 - Moritz, CA

PB - IEEE Society

CY - Piscataway, NJ, USA

T2 - NANOARCH 2014, Paris, France

Y2 - 8 July 2014 through 10 July 2014

ER -