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Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era. / Majzoub, Sohaib; Saleh, Resve A.; Ashraf, Imran; Taouil, Mottaqiallah; Hamdioui, Said.

In: IEEE Access, Vol. 7, 8648367, 2019, p. 33115-33129.

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Majzoub, Sohaib ; Saleh, Resve A. ; Ashraf, Imran ; Taouil, Mottaqiallah ; Hamdioui, Said. / Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era. In: IEEE Access. 2019 ; Vol. 7. pp. 33115-33129.

BibTeX

@article{322ea5ca5c4f4c748dc21ec9f222a46c,
title = "Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era",
abstract = " In this paper, we study the impact of the idle/dynamic power consumption ratio on the effectiveness of a multi-V dd /frequency manycore design. We propose a new tool called LVSiM (a Low-Power and Variation-Aware Manycore Simulator) to carry out the experiments. It is a novel manycore simulator targeted towards low-power optimization methods including within-die process and workload variations. LVSiM provides a holistic platform for multi-V dd /frequency voltage island analysis, optimization, and design. It provides a tool for the early design exploration stage to analyze large-scale manycores with a given number of cores on 3D-stacked layers, network-on-chip communication busses, technology parameters, voltage and frequency values, and power grid parameters, using a variety of different optimization methods. LVSiM has been calibrated with Sniper/McPAT at a nominal frequency, and then the energy-delay-product (EDP) numbers were compared after frequency scaling. The average error is shown to be 10% after frequency scaling, which is sufficient for our purposes. The experiments in this work are carried out for different Idle/Dynamic ratios considering 1260 benchmarks with task sizes ranging from 4000 to 16 000 executing on 3200 cores. The best configurations are shown to produce on average 20.7% to 24.6% EDP savings compared to the nominal configuration. Traditional scheduling methods are used in the nominal configuration with the unused cores switched off. In addition, we show that, as the Idle/Dynamic ratio increases, the multi-V dd /frequency approach becomes less effective. In the case of a high Idle/Dynamic ratio, the minimum EDP can be achieved through switching off unused cores as opposed to using a multi-V dd /frequency approach. This conclusion is important, especially in the dark-silicon era, where switching cores on and/or off as needed is a common practice. ",
keywords = "3D-stacked chip, dark-silicon, dynamic power, energy-delay-product, frequency scaling, idle power, low-power design, manycore, multicore, process variation, simulator, voltage scaling, voltage selection, within-die variation",
author = "Sohaib Majzoub and Saleh, {Resve A.} and Imran Ashraf and Mottaqiallah Taouil and Said Hamdioui",
year = "2019",
doi = "10.1109/ACCESS.2019.2900477",
language = "English",
volume = "7",
pages = "33115--33129",
journal = "IEEE Access",
issn = "2169-3536",
publisher = "IEEE",

}

RIS

TY - JOUR

T1 - Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

AU - Majzoub, Sohaib

AU - Saleh, Resve A.

AU - Ashraf, Imran

AU - Taouil, Mottaqiallah

AU - Hamdioui, Said

PY - 2019

Y1 - 2019

N2 - In this paper, we study the impact of the idle/dynamic power consumption ratio on the effectiveness of a multi-V dd /frequency manycore design. We propose a new tool called LVSiM (a Low-Power and Variation-Aware Manycore Simulator) to carry out the experiments. It is a novel manycore simulator targeted towards low-power optimization methods including within-die process and workload variations. LVSiM provides a holistic platform for multi-V dd /frequency voltage island analysis, optimization, and design. It provides a tool for the early design exploration stage to analyze large-scale manycores with a given number of cores on 3D-stacked layers, network-on-chip communication busses, technology parameters, voltage and frequency values, and power grid parameters, using a variety of different optimization methods. LVSiM has been calibrated with Sniper/McPAT at a nominal frequency, and then the energy-delay-product (EDP) numbers were compared after frequency scaling. The average error is shown to be 10% after frequency scaling, which is sufficient for our purposes. The experiments in this work are carried out for different Idle/Dynamic ratios considering 1260 benchmarks with task sizes ranging from 4000 to 16 000 executing on 3200 cores. The best configurations are shown to produce on average 20.7% to 24.6% EDP savings compared to the nominal configuration. Traditional scheduling methods are used in the nominal configuration with the unused cores switched off. In addition, we show that, as the Idle/Dynamic ratio increases, the multi-V dd /frequency approach becomes less effective. In the case of a high Idle/Dynamic ratio, the minimum EDP can be achieved through switching off unused cores as opposed to using a multi-V dd /frequency approach. This conclusion is important, especially in the dark-silicon era, where switching cores on and/or off as needed is a common practice.

AB - In this paper, we study the impact of the idle/dynamic power consumption ratio on the effectiveness of a multi-V dd /frequency manycore design. We propose a new tool called LVSiM (a Low-Power and Variation-Aware Manycore Simulator) to carry out the experiments. It is a novel manycore simulator targeted towards low-power optimization methods including within-die process and workload variations. LVSiM provides a holistic platform for multi-V dd /frequency voltage island analysis, optimization, and design. It provides a tool for the early design exploration stage to analyze large-scale manycores with a given number of cores on 3D-stacked layers, network-on-chip communication busses, technology parameters, voltage and frequency values, and power grid parameters, using a variety of different optimization methods. LVSiM has been calibrated with Sniper/McPAT at a nominal frequency, and then the energy-delay-product (EDP) numbers were compared after frequency scaling. The average error is shown to be 10% after frequency scaling, which is sufficient for our purposes. The experiments in this work are carried out for different Idle/Dynamic ratios considering 1260 benchmarks with task sizes ranging from 4000 to 16 000 executing on 3200 cores. The best configurations are shown to produce on average 20.7% to 24.6% EDP savings compared to the nominal configuration. Traditional scheduling methods are used in the nominal configuration with the unused cores switched off. In addition, we show that, as the Idle/Dynamic ratio increases, the multi-V dd /frequency approach becomes less effective. In the case of a high Idle/Dynamic ratio, the minimum EDP can be achieved through switching off unused cores as opposed to using a multi-V dd /frequency approach. This conclusion is important, especially in the dark-silicon era, where switching cores on and/or off as needed is a common practice.

KW - 3D-stacked chip

KW - dark-silicon

KW - dynamic power

KW - energy-delay-product

KW - frequency scaling

KW - idle power

KW - low-power design

KW - manycore

KW - multicore

KW - process variation

KW - simulator

KW - voltage scaling

KW - voltage selection

KW - within-die variation

UR - http://www.scopus.com/inward/record.url?scp=85063573998&partnerID=8YFLogxK

U2 - 10.1109/ACCESS.2019.2900477

DO - 10.1109/ACCESS.2019.2900477

M3 - Article

AN - SCOPUS:85063573998

VL - 7

SP - 33115

EP - 33129

JO - IEEE Access

JF - IEEE Access

SN - 2169-3536

M1 - 8648367

ER -

ID: 52909262