Standard

Error Correction Code protected Data Processing Units. / Cucu Laurenciu, Nicoleta; Gupta, Tushar; Savin, Valentin; Cotofana, Sorin.

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). ed. / W. Zhao; C.A. Moritz. New York : Association for Computing Machinery (ACM), 2016. p. 37-42.

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Cucu Laurenciu, N, Gupta, T, Savin, V & Cotofana, S 2016, Error Correction Code protected Data Processing Units. in W Zhao & CA Moritz (eds), 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Association for Computing Machinery (ACM), New York, pp. 37-42, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Beijing, China, 18/07/16.

APA

Cucu Laurenciu, N., Gupta, T., Savin, V., & Cotofana, S. (2016). Error Correction Code protected Data Processing Units. In W. Zhao, & C. A. Moritz (Eds.), 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (pp. 37-42). New York: Association for Computing Machinery (ACM).

Vancouver

Cucu Laurenciu N, Gupta T, Savin V, Cotofana S. Error Correction Code protected Data Processing Units. In Zhao W, Moritz CA, editors, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). New York: Association for Computing Machinery (ACM). 2016. p. 37-42

Author

Cucu Laurenciu, Nicoleta ; Gupta, Tushar ; Savin, Valentin ; Cotofana, Sorin. / Error Correction Code protected Data Processing Units. 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). editor / W. Zhao ; C.A. Moritz. New York : Association for Computing Machinery (ACM), 2016. pp. 37-42

BibTeX

@inproceedings{fc3040bd53d6444db01619f76ad12e5a,
title = "Error Correction Code protected Data Processing Units",
abstract = "The significant uncertainty associated with current nanodevices fabrication and operation, calls for a circuit design paradigm change, which ought to actively embrace the inherently nanodevice unreliability to generate overall circuit architectures able to perform reliable computation. While for data storage units viable solutions exist, Data Processing Units (DPUs) are not amenable to a similar line of reasoning. The typical approach undertaken for fault-tolerant DPUs relies on modular redundancy (e.g., spatial, temporal), which while being effective from an error tolerance perspective, generally involves high area and/or performance impairments. This paper proposes a generic methodology to obtain reliable DPU implementations built with unreliable components by intimately intertwining Error Correcting Codes (ECCs) codecs with the DPU functionality. The ECC protected DPU architecture is derived cluster-wise with area and reliability constraints, by exploiting dependence relations (logical and w.r.t. shared area) between internal signals pertaining to the DPU and the ECC codec. To evaluate the error rate and performance implications, a multitude of test corners were considered (e.g., gate criticality, ECC type and structure, faulty and low complexity decoder, time-space redundancy) for an ECC protected 6-bit adder architecture. Simulation results reveal that the ECC embedding approach can be effective from both error rate and area perspective, for the Pareto designs with performance figures of merit situated in-between consecutive modular redundancy based design corresponding curves. The proposed approach is generic from the coding point of view, scalable, and enables a fine grained control of the DPU desired reliability degree and area overhead.",
keywords = "reliable computing, unreliable devices, ECC, reliable functional units",
author = "{Cucu Laurenciu}, Nicoleta and Tushar Gupta and Valentin Savin and Sorin Cotofana",
year = "2016",
language = "English",
isbn = "978-1-4673-8927-3",
pages = "37--42",
editor = "W. Zhao and C.A. Moritz",
booktitle = "2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)",
publisher = "Association for Computing Machinery (ACM)",
address = "United States",

}

RIS

TY - GEN

T1 - Error Correction Code protected Data Processing Units

AU - Cucu Laurenciu, Nicoleta

AU - Gupta, Tushar

AU - Savin, Valentin

AU - Cotofana, Sorin

PY - 2016

Y1 - 2016

N2 - The significant uncertainty associated with current nanodevices fabrication and operation, calls for a circuit design paradigm change, which ought to actively embrace the inherently nanodevice unreliability to generate overall circuit architectures able to perform reliable computation. While for data storage units viable solutions exist, Data Processing Units (DPUs) are not amenable to a similar line of reasoning. The typical approach undertaken for fault-tolerant DPUs relies on modular redundancy (e.g., spatial, temporal), which while being effective from an error tolerance perspective, generally involves high area and/or performance impairments. This paper proposes a generic methodology to obtain reliable DPU implementations built with unreliable components by intimately intertwining Error Correcting Codes (ECCs) codecs with the DPU functionality. The ECC protected DPU architecture is derived cluster-wise with area and reliability constraints, by exploiting dependence relations (logical and w.r.t. shared area) between internal signals pertaining to the DPU and the ECC codec. To evaluate the error rate and performance implications, a multitude of test corners were considered (e.g., gate criticality, ECC type and structure, faulty and low complexity decoder, time-space redundancy) for an ECC protected 6-bit adder architecture. Simulation results reveal that the ECC embedding approach can be effective from both error rate and area perspective, for the Pareto designs with performance figures of merit situated in-between consecutive modular redundancy based design corresponding curves. The proposed approach is generic from the coding point of view, scalable, and enables a fine grained control of the DPU desired reliability degree and area overhead.

AB - The significant uncertainty associated with current nanodevices fabrication and operation, calls for a circuit design paradigm change, which ought to actively embrace the inherently nanodevice unreliability to generate overall circuit architectures able to perform reliable computation. While for data storage units viable solutions exist, Data Processing Units (DPUs) are not amenable to a similar line of reasoning. The typical approach undertaken for fault-tolerant DPUs relies on modular redundancy (e.g., spatial, temporal), which while being effective from an error tolerance perspective, generally involves high area and/or performance impairments. This paper proposes a generic methodology to obtain reliable DPU implementations built with unreliable components by intimately intertwining Error Correcting Codes (ECCs) codecs with the DPU functionality. The ECC protected DPU architecture is derived cluster-wise with area and reliability constraints, by exploiting dependence relations (logical and w.r.t. shared area) between internal signals pertaining to the DPU and the ECC codec. To evaluate the error rate and performance implications, a multitude of test corners were considered (e.g., gate criticality, ECC type and structure, faulty and low complexity decoder, time-space redundancy) for an ECC protected 6-bit adder architecture. Simulation results reveal that the ECC embedding approach can be effective from both error rate and area perspective, for the Pareto designs with performance figures of merit situated in-between consecutive modular redundancy based design corresponding curves. The proposed approach is generic from the coding point of view, scalable, and enables a fine grained control of the DPU desired reliability degree and area overhead.

KW - reliable computing

KW - unreliable devices

KW - ECC

KW - reliable functional units

M3 - Conference contribution

SN - 978-1-4673-8927-3

SP - 37

EP - 42

BT - 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

A2 - Zhao, W.

A2 - Moritz, C.A.

PB - Association for Computing Machinery (ACM)

CY - New York

ER -

ID: 10611346