Standard

Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors. / Sartor, A. L.; Lorenzon, A. F; Carro, Luigi; Kastensmidt, Fernanda; Wong, S.; Beck, Antonio C.S.

In: ACM Journal on Emerging Technologies in Computing Systems, Vol. 13, No. 2, 2017, p. 13:1-13:21.

Research output: Contribution to journalSpecial issueScientificpeer-review

Harvard

Sartor, AL, Lorenzon, AF, Carro, L, Kastensmidt, F, Wong, S & Beck, ACS 2017, 'Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors' ACM Journal on Emerging Technologies in Computing Systems, vol. 13, no. 2, pp. 13:1-13:21. https://doi.org/10.1145/3001935

APA

Sartor, A. L., Lorenzon, A. F., Carro, L., Kastensmidt, F., Wong, S., & Beck, A. C. S. (2017). Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors. ACM Journal on Emerging Technologies in Computing Systems, 13(2), 13:1-13:21. https://doi.org/10.1145/3001935

Vancouver

Sartor AL, Lorenzon AF, Carro L, Kastensmidt F, Wong S, Beck ACS. Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors. ACM Journal on Emerging Technologies in Computing Systems. 2017;13(2):13:1-13:21. https://doi.org/10.1145/3001935

Author

Sartor, A. L. ; Lorenzon, A. F ; Carro, Luigi ; Kastensmidt, Fernanda ; Wong, S. ; Beck, Antonio C.S. / Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors. In: ACM Journal on Emerging Technologies in Computing Systems. 2017 ; Vol. 13, No. 2. pp. 13:1-13:21.

BibTeX

@article{2c25495342b94cf9a26372ab9e686b32,
title = "Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors",
abstract = "Because of technology scaling, the soft error rate has been increasing in digital circuits, which affects system reliability. Therefore, modern processors, including VLIW architectures, must have means to mitigate such effects to guarantee reliable computing. In this scenario, our work proposes three low overhead fault tolerance approaches based on instruction duplication with zero latency detection, which uses a rollback mechanism to correct soft errors in the pipelanes of a configurable VLIW processor. The first uses idle issue slots within a period of time to execute extra instructions considering distinct application phases. The second works at a finer grain, adaptively exploiting idle functional units at run-time. However, some applications present high instruction-level parallelism (ILP), so the ability to provide fault tolerance is reduced: less functional units will be idle, decreasing the number of potential duplicated instructions. The third approach attacks this issue by dynamically reducing ILP according to a configurable threshold, increasing fault tolerance at the cost of performance. While the first two approaches achieve significant fault coverage with minimal area and power overhead for applications with low ILP, the latter improves fault tolerance with low performance degradation. All approaches are evaluated considering area, performance, power dissipation, and error coverage.",
keywords = "Fault tolerance, VLIW, soft errors, adaptive processor",
author = "Sartor, {A. L.} and Lorenzon, {A. F} and Luigi Carro and Fernanda Kastensmidt and S. Wong and Beck, {Antonio C.S.}",
note = "Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era and Regular Papers",
year = "2017",
doi = "10.1145/3001935",
language = "English",
volume = "13",
pages = "13:1--13:21",
journal = "ACM Journal on Emerging Technologies in Computing Systems",
issn = "1550-4832",
publisher = "Association for Computing Machinery (ACM)",
number = "2",

}

RIS

TY - JOUR

T1 - Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors

AU - Sartor, A. L.

AU - Lorenzon, A. F

AU - Carro, Luigi

AU - Kastensmidt, Fernanda

AU - Wong, S.

AU - Beck, Antonio C.S.

N1 - Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era and Regular Papers

PY - 2017

Y1 - 2017

N2 - Because of technology scaling, the soft error rate has been increasing in digital circuits, which affects system reliability. Therefore, modern processors, including VLIW architectures, must have means to mitigate such effects to guarantee reliable computing. In this scenario, our work proposes three low overhead fault tolerance approaches based on instruction duplication with zero latency detection, which uses a rollback mechanism to correct soft errors in the pipelanes of a configurable VLIW processor. The first uses idle issue slots within a period of time to execute extra instructions considering distinct application phases. The second works at a finer grain, adaptively exploiting idle functional units at run-time. However, some applications present high instruction-level parallelism (ILP), so the ability to provide fault tolerance is reduced: less functional units will be idle, decreasing the number of potential duplicated instructions. The third approach attacks this issue by dynamically reducing ILP according to a configurable threshold, increasing fault tolerance at the cost of performance. While the first two approaches achieve significant fault coverage with minimal area and power overhead for applications with low ILP, the latter improves fault tolerance with low performance degradation. All approaches are evaluated considering area, performance, power dissipation, and error coverage.

AB - Because of technology scaling, the soft error rate has been increasing in digital circuits, which affects system reliability. Therefore, modern processors, including VLIW architectures, must have means to mitigate such effects to guarantee reliable computing. In this scenario, our work proposes three low overhead fault tolerance approaches based on instruction duplication with zero latency detection, which uses a rollback mechanism to correct soft errors in the pipelanes of a configurable VLIW processor. The first uses idle issue slots within a period of time to execute extra instructions considering distinct application phases. The second works at a finer grain, adaptively exploiting idle functional units at run-time. However, some applications present high instruction-level parallelism (ILP), so the ability to provide fault tolerance is reduced: less functional units will be idle, decreasing the number of potential duplicated instructions. The third approach attacks this issue by dynamically reducing ILP according to a configurable threshold, increasing fault tolerance at the cost of performance. While the first two approaches achieve significant fault coverage with minimal area and power overhead for applications with low ILP, the latter improves fault tolerance with low performance degradation. All approaches are evaluated considering area, performance, power dissipation, and error coverage.

KW - Fault tolerance

KW - VLIW

KW - soft errors

KW - adaptive processor

U2 - 10.1145/3001935

DO - 10.1145/3001935

M3 - Special issue

VL - 13

SP - 13:1-13:21

JO - ACM Journal on Emerging Technologies in Computing Systems

T2 - ACM Journal on Emerging Technologies in Computing Systems

JF - ACM Journal on Emerging Technologies in Computing Systems

SN - 1550-4832

IS - 2

ER -

ID: 31194952