Standard

Exploring ILP and TLP on a Polymorphic VLIW Processor. / Brandon, Anthony; Hoozemans, Joost; van Straten, Jeroen; Wong, Stephan.

Architecture of Computing Systems - ARCS 2017: 30th International Conference Proceedings. ed. / J. Knoop; W. Karl; M. Schulz; K. Inoue; T. Pionteck. Cham : Springer, 2017. p. 177-189 (Lecture Notes in Computer Science ; Vol. 10172).

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Brandon, A, Hoozemans, J, van Straten, J & Wong, S 2017, Exploring ILP and TLP on a Polymorphic VLIW Processor. in J Knoop, W Karl, M Schulz, K Inoue & T Pionteck (eds), Architecture of Computing Systems - ARCS 2017: 30th International Conference Proceedings. Lecture Notes in Computer Science , vol. 10172, Springer, Cham, pp. 177-189, Architecture of Computing Systems, ARCS 2017, Vienna, Austria, 3/04/17. https://doi.org/10.1007/978-3-319-54999-6_14

APA

Brandon, A., Hoozemans, J., van Straten, J., & Wong, S. (2017). Exploring ILP and TLP on a Polymorphic VLIW Processor. In J. Knoop, W. Karl, M. Schulz, K. Inoue, & T. Pionteck (Eds.), Architecture of Computing Systems - ARCS 2017: 30th International Conference Proceedings (pp. 177-189). (Lecture Notes in Computer Science ; Vol. 10172). Cham: Springer. https://doi.org/10.1007/978-3-319-54999-6_14

Vancouver

Brandon A, Hoozemans J, van Straten J, Wong S. Exploring ILP and TLP on a Polymorphic VLIW Processor. In Knoop J, Karl W, Schulz M, Inoue K, Pionteck T, editors, Architecture of Computing Systems - ARCS 2017: 30th International Conference Proceedings. Cham: Springer. 2017. p. 177-189. (Lecture Notes in Computer Science ). https://doi.org/10.1007/978-3-319-54999-6_14

Author

Brandon, Anthony ; Hoozemans, Joost ; van Straten, Jeroen ; Wong, Stephan. / Exploring ILP and TLP on a Polymorphic VLIW Processor. Architecture of Computing Systems - ARCS 2017: 30th International Conference Proceedings. editor / J. Knoop ; W. Karl ; M. Schulz ; K. Inoue ; T. Pionteck. Cham : Springer, 2017. pp. 177-189 (Lecture Notes in Computer Science ).

BibTeX

@inproceedings{fc5a359b081b4981ae93835d043767db,
title = "Exploring ILP and TLP on a Polymorphic VLIW Processor",
abstract = "In today’s computing environments, the concurrent execution of multiple applications/threads is common and multi-cores are verywell-suited to handle such workloads. However, they suffer from the fact that any mismatch between the application’s inherent instruction-level parallelism (ILP) and the core’s parallelism leads to unused resources or loss in performance. An accepted solution is to include several types of cores and match them dynamically depending on the performance needs of the application. This approach becomes less efficient when the number of cores does not match the number of parallel threads. Furthermore,the heterogeneity of (fixed) cores cannot be increased indefinitely as it would result in even higher degrees of mismatching and increased movement of instruction and data streams. In this paper, we are proposing a polymorphic processor, based on VLIW architectures, that can adapt its issue-width during runtime. By design, the processor can be perceived as a single wide core (8-issue VLIW) or two medium-wide cores (4-issue) or four small cores (2-issue) that can run high-ILP/low DLP, medium-ILP/medium DLP, and low-ILP/high-DLP applications, respectively. Furthermore, we are executing one single generic binary while performing these reconfigurations. In order to show the effectiveness of our approach, we synthesized different versions of the core to represent fixed heterogeneous cores and compared them to the dynamic implementation of the core. Our experiments show that the dynamically adaptive solution performs on average 7{\%} faster and uses 5{\%} less area than a platform which consists of fixed cores with 1.5× as many datapaths.",
author = "Anthony Brandon and Joost Hoozemans and {van Straten}, Jeroen and Stephan Wong",
year = "2017",
doi = "10.1007/978-3-319-54999-6_14",
language = "English",
isbn = "978-3-319-54998-9",
series = "Lecture Notes in Computer Science",
publisher = "Springer",
pages = "177--189",
editor = "J. Knoop and W. Karl and M. Schulz and K. Inoue and T. Pionteck",
booktitle = "Architecture of Computing Systems - ARCS 2017",

}

RIS

TY - GEN

T1 - Exploring ILP and TLP on a Polymorphic VLIW Processor

AU - Brandon, Anthony

AU - Hoozemans, Joost

AU - van Straten, Jeroen

AU - Wong, Stephan

PY - 2017

Y1 - 2017

N2 - In today’s computing environments, the concurrent execution of multiple applications/threads is common and multi-cores are verywell-suited to handle such workloads. However, they suffer from the fact that any mismatch between the application’s inherent instruction-level parallelism (ILP) and the core’s parallelism leads to unused resources or loss in performance. An accepted solution is to include several types of cores and match them dynamically depending on the performance needs of the application. This approach becomes less efficient when the number of cores does not match the number of parallel threads. Furthermore,the heterogeneity of (fixed) cores cannot be increased indefinitely as it would result in even higher degrees of mismatching and increased movement of instruction and data streams. In this paper, we are proposing a polymorphic processor, based on VLIW architectures, that can adapt its issue-width during runtime. By design, the processor can be perceived as a single wide core (8-issue VLIW) or two medium-wide cores (4-issue) or four small cores (2-issue) that can run high-ILP/low DLP, medium-ILP/medium DLP, and low-ILP/high-DLP applications, respectively. Furthermore, we are executing one single generic binary while performing these reconfigurations. In order to show the effectiveness of our approach, we synthesized different versions of the core to represent fixed heterogeneous cores and compared them to the dynamic implementation of the core. Our experiments show that the dynamically adaptive solution performs on average 7% faster and uses 5% less area than a platform which consists of fixed cores with 1.5× as many datapaths.

AB - In today’s computing environments, the concurrent execution of multiple applications/threads is common and multi-cores are verywell-suited to handle such workloads. However, they suffer from the fact that any mismatch between the application’s inherent instruction-level parallelism (ILP) and the core’s parallelism leads to unused resources or loss in performance. An accepted solution is to include several types of cores and match them dynamically depending on the performance needs of the application. This approach becomes less efficient when the number of cores does not match the number of parallel threads. Furthermore,the heterogeneity of (fixed) cores cannot be increased indefinitely as it would result in even higher degrees of mismatching and increased movement of instruction and data streams. In this paper, we are proposing a polymorphic processor, based on VLIW architectures, that can adapt its issue-width during runtime. By design, the processor can be perceived as a single wide core (8-issue VLIW) or two medium-wide cores (4-issue) or four small cores (2-issue) that can run high-ILP/low DLP, medium-ILP/medium DLP, and low-ILP/high-DLP applications, respectively. Furthermore, we are executing one single generic binary while performing these reconfigurations. In order to show the effectiveness of our approach, we synthesized different versions of the core to represent fixed heterogeneous cores and compared them to the dynamic implementation of the core. Our experiments show that the dynamically adaptive solution performs on average 7% faster and uses 5% less area than a platform which consists of fixed cores with 1.5× as many datapaths.

U2 - 10.1007/978-3-319-54999-6_14

DO - 10.1007/978-3-319-54999-6_14

M3 - Conference contribution

SN - 978-3-319-54998-9

T3 - Lecture Notes in Computer Science

SP - 177

EP - 189

BT - Architecture of Computing Systems - ARCS 2017

A2 - Knoop, J.

A2 - Karl, W.

A2 - Schulz, M.

A2 - Inoue, K.

A2 - Pionteck, T.

PB - Springer

CY - Cham

ER -

ID: 30883355