• Jiajie Fan
  • Aihua Hu
  • Michael Pecht
  • Wei Chen
  • Xuejun Fan
  • Dan Xu
  • Guoqi Zhang

As one of solid state lighting sources, wafer-level chip scale Light Emitting Diode (LED) packages has gained much attention, because of its compact size, high power and high optical performance. For this package to be effective, the solder layer plays the critical role in heat dissipation, mechanical support and electrical conductivity. Among all types of solder materials, Sn-3.0Ag-0.5Cu (SAC305) solder alloy is considered as one of best chip-attachment candidates due to its acceptable cost, good solderability, and favorable shear strength. However, such solder connections are prone to fatigue over time due to thermal or power cycling. This paper models the wafer level chip scale LEDs soldered on both aluminum oxide and aluminum substrates with SAC305 solder alloy. Thermal cycling conditions are simulated to assess the fatigue damage of the solder interconnection. Von Mises stress and plastic work density are utilized to represent the fatigue damage per cycle by using finite element analysis (FEA) method. Important design considerations include the effects of LED chip substrate, thickness of the solder interconnections, void ratio in the solder connections and PCB substrate. The result is a set of fatigue damage accumulation metrics.

Original languageEnglish
Title of host publicationProceedings - 2018 19th International Conference on Electronic Packaging Technology, ICEPT 2018
EditorsF. Xiao, J. Wang, L. Chen, T. Ye
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages1642-1648
Number of pages7
ISBN (Electronic)978-1-5386-6386-8
DOIs
Publication statusPublished - 2018
EventICEPT 2018: 19th International Conference on Electronic Packaging Technology - Shanghai, China
Duration: 8 Aug 201811 Aug 2018
Conference number: 19

Conference

ConferenceICEPT 2018
CountryChina
CityShanghai
Period8/08/1811/08/18

    Research areas

  • finite element model, flip chip, Light-emitting diodes, solder layer, WLCSP

ID: 47551374