DOI

  • Thien T. Nguyen-Ly
  • Tushar Gupta
  • Manuel Pezzin
  • Valentin Savin
  • David Declercq
  • Sorin Cotofana
In this paper, we propose a layered LDPC decoder architecture targeting flexibility, high-throughput, low cost, and efficient use of the hardware resources. The proposed architecture provides full design time flexibility, i.e., it can accommodate any Quasi-Cyclic (QC) LDPC code, and also allows redefining a number of parameters of the QC-LDPC code at the run time. The main novelty of the paper consists of: a new low-cost processing unit that merges the logical functionalities of the Variable-Node Unit (VNU) and the A Posteriori Log-Likelihood Ratio (AP-LLR) unit in an efficient way, a high speed, low-cost Check-Node Unit (CNU) architecture, which is executed twice at each iteration in order to complete the computation of the check-node messages, a splitting of the iteration processing in two perfectly symmetric stages, executed in two consecutive clock cycles, each one using exactly the same processing resources, the processing load is perfectly balanced between the two clock cycles, thus yielding an optimal clock frequency. Synthesis results targeting a 65nm CMOS technology for a (3,6)-regular (648,1296) Quasi-Cyclic LDPC code and for the WiMax (1152,2304) irregular QC-LDPC code show significant improvements in terms of area and throughput compared to the baseline architecture discussed in this paper, as well as several state of the art implementations.
Original languageEnglish
Title of host publicationProceedings - 19th Euromicro Conference on Digital System Design (DSD 2016)
EditorsParis Kitsos
Place of PublicationPiscataway
PublisherIEEE
Pages230-237
Number of pages7
ISBN (Print)978-1-5090-2817-7
DOIs
Publication statusPublished - 2016
Event19th Euromicro Conference on Digital Systems Design: Euromicro DSD/SEAA 2016 - St. Raphael Hotel, Limassol, Cyprus
Duration: 31 Aug 20162 Sep 2016

Conference

Conference19th Euromicro Conference on Digital Systems Design
Abbreviated titleDSD 2016
CountryCyprus
CityLimassol
Period31/08/162/09/16

    Research areas

  • Flexibility, QC-LDPC codes, Layered architecture, High-throughput, Low-cost

ID: 10299745