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Hardware-based aging mitigation scheme for memory address decoder. / Kraak, Daniel; Agbo, Innocent; Taouil, Mottaqiallah; Hamdioui, Said; Weckx, Pieter; Cosemans, Stefan; Catthoor, Francky.

2019 IEEE European Test Symposium (ETS). IEEE, 2019. p. 1-6.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Harvard

Kraak, D, Agbo, I, Taouil, M, Hamdioui, S, Weckx, P, Cosemans, S & Catthoor, F 2019, Hardware-based aging mitigation scheme for memory address decoder. in 2019 IEEE European Test Symposium (ETS). IEEE, pp. 1-6, 24th IEEE European Test Symposium 2019, Baden-Baden, Germany, 27/05/19. https://doi.org/10.1109/ETS.2019.8791536

APA

Kraak, D., Agbo, I., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S., & Catthoor, F. (2019). Hardware-based aging mitigation scheme for memory address decoder. In 2019 IEEE European Test Symposium (ETS) (pp. 1-6). IEEE. https://doi.org/10.1109/ETS.2019.8791536

Vancouver

Kraak D, Agbo I, Taouil M, Hamdioui S, Weckx P, Cosemans S et al. Hardware-based aging mitigation scheme for memory address decoder. In 2019 IEEE European Test Symposium (ETS). IEEE. 2019. p. 1-6 https://doi.org/10.1109/ETS.2019.8791536

Author

Kraak, Daniel ; Agbo, Innocent ; Taouil, Mottaqiallah ; Hamdioui, Said ; Weckx, Pieter ; Cosemans, Stefan ; Catthoor, Francky. / Hardware-based aging mitigation scheme for memory address decoder. 2019 IEEE European Test Symposium (ETS). IEEE, 2019. pp. 1-6

BibTeX

@inproceedings{5051e76b6d55445abcef8a367505be4b,
title = "Hardware-based aging mitigation scheme for memory address decoder",
abstract = "Designers typically add design margins to memories to compensate for their aging. As the aging impact increases with technology scaling, bigger margins become necessary. However, this negatively impacts area, yield, performance, and power consumption. Alternatively, mitigation schemes can be used to reduce the impact of aging. This paper proposes a hardware-based mitigation scheme for the memory's address decoder logic. The scheme is based on adapting the decoder's workload during idle cycles by stressing the short paths and putting long paths into relaxation. Thanks to the adapted workload, the impact of aging on the address decoder is reduced, resulting in a more reliable memory. To validate the benefit of the mitigation scheme, the decoder's degradation of the L1 data and instruction caches for an ARM v8-a processor is analyzed. The experimental results show that the proposed mitigation scheme reduces the degradation of the decoder's timing margin with up to 4.1x at negligible area and no more than 3% power overhead.",
keywords = "Address decoder, Aging, Memory, Mitigation",
author = "Daniel Kraak and Innocent Agbo and Mottaqiallah Taouil and Said Hamdioui and Pieter Weckx and Stefan Cosemans and Francky Catthoor",
year = "2019",
doi = "10.1109/ETS.2019.8791536",
language = "English",
isbn = "978-1-7281-1174-2",
pages = "1--6",
booktitle = "2019 IEEE European Test Symposium (ETS)",
publisher = "IEEE",
address = "United States",
note = "24th IEEE European Test Symposium 2019, ETS ; Conference date: 27-05-2019 Through 31-05-2019",
url = "http://www.testgroup.polito.it/ets19",

}

RIS

TY - GEN

T1 - Hardware-based aging mitigation scheme for memory address decoder

AU - Kraak, Daniel

AU - Agbo, Innocent

AU - Taouil, Mottaqiallah

AU - Hamdioui, Said

AU - Weckx, Pieter

AU - Cosemans, Stefan

AU - Catthoor, Francky

N1 - Conference code: 24th

PY - 2019

Y1 - 2019

N2 - Designers typically add design margins to memories to compensate for their aging. As the aging impact increases with technology scaling, bigger margins become necessary. However, this negatively impacts area, yield, performance, and power consumption. Alternatively, mitigation schemes can be used to reduce the impact of aging. This paper proposes a hardware-based mitigation scheme for the memory's address decoder logic. The scheme is based on adapting the decoder's workload during idle cycles by stressing the short paths and putting long paths into relaxation. Thanks to the adapted workload, the impact of aging on the address decoder is reduced, resulting in a more reliable memory. To validate the benefit of the mitigation scheme, the decoder's degradation of the L1 data and instruction caches for an ARM v8-a processor is analyzed. The experimental results show that the proposed mitigation scheme reduces the degradation of the decoder's timing margin with up to 4.1x at negligible area and no more than 3% power overhead.

AB - Designers typically add design margins to memories to compensate for their aging. As the aging impact increases with technology scaling, bigger margins become necessary. However, this negatively impacts area, yield, performance, and power consumption. Alternatively, mitigation schemes can be used to reduce the impact of aging. This paper proposes a hardware-based mitigation scheme for the memory's address decoder logic. The scheme is based on adapting the decoder's workload during idle cycles by stressing the short paths and putting long paths into relaxation. Thanks to the adapted workload, the impact of aging on the address decoder is reduced, resulting in a more reliable memory. To validate the benefit of the mitigation scheme, the decoder's degradation of the L1 data and instruction caches for an ARM v8-a processor is analyzed. The experimental results show that the proposed mitigation scheme reduces the degradation of the decoder's timing margin with up to 4.1x at negligible area and no more than 3% power overhead.

KW - Address decoder

KW - Aging

KW - Memory

KW - Mitigation

UR - http://www.scopus.com/inward/record.url?scp=85071149751&partnerID=8YFLogxK

U2 - 10.1109/ETS.2019.8791536

DO - 10.1109/ETS.2019.8791536

M3 - Conference contribution

AN - SCOPUS:85071149751

SN - 978-1-7281-1174-2

SP - 1

EP - 6

BT - 2019 IEEE European Test Symposium (ETS)

PB - IEEE

T2 - 24th IEEE European Test Symposium 2019

Y2 - 27 May 2019 through 31 May 2019

ER -

ID: 57425573