Highly Efficient and Linear Class-E CMOS Digital Power Amplifier Using a Compensated Marchand Balun and Circuit-Level Linearization Achieving 67% Peak DE and -40dBc ACLR without DPD

Mohsen Hashemi; Lei Zhou; Yiyu Shen; Mohammadreza Mehrpoo; Leo de Vreede

doi:10.1109/MWSYM.2017.8059066

Highly Efficient and Linear Class-E CMOS Digital Power Amplifier Using a Compensated Marchand Balun and Circuit-Level Linearization Achieving 67% Peak DE and -40dBc ACLR without DPD

Mohsen Hashemi, Lei Zhou, Yiyu Shen, Mohammadreza Mehrpoo, Leo de Vreede

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

4 Citations (Scopus)

Abstract

A highly efficient and linear wideband digital polar CMOS class-E power amplifier (DPA) is presented. Using a compensated wideband Marchand balun with re-entrant coupled lines for the output matching network, more than 50% peak drain efficiency over 2.2-3GHz with 16-17dBm Pout are achieved. The linearity is significantly improved by nonlinearly sizing the DPA array along with overdrive-voltage control and concurrent multiphase RF clocking. The chip prototype is fabricated in 40nm bulk CMOS and the balun is fabricated on a two-layer PCB. Measured results show -40dBc for a 40MHz QAM signal at 2.6GHz without using any sort of DPD. The measured peak Pout, DE and PAE at 2.6GHz are 17.2dBm, 67% and 45% with VDD=0.7V.

Original language	English
Title of host publication	2017 IEEE MTT-S International Microwave Symposium (IMS)
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	2025 – 2028
Number of pages	4
ISBN (Electronic)	978-1-5090-6360-4
DOIs	https://doi.org/10.1109/MWSYM.2017.8059066
Publication status	Published - 2017
Event	IEEE MTT-S International Microwave Symposium, IMS 2017: Connecting Minds. Exchanging Ideas - Hawaii Convention Center, Honolulu, HI, United States Duration: 4 Jun 2017 → 9 Jun 2017 https://ims2017.org/

Conference

Conference	IEEE MTT-S International Microwave Symposium, IMS 2017
Abbreviated title	IMS 2017
Country/Territory	United States
City	Honolulu, HI
Period	4/06/17 → 9/06/17
Internet address	https://ims2017.org/

Keywords

Class-E
CMOS
digital PA
DPD-less
efficient
linear
wideband

Access to Document

10.1109/MWSYM.2017.8059066

4 Citations
1 Dissertation (TU Delft)

Energy Efficient and Intrinsically Linear Digital Polar Transmitters
Hashemi, M., 2020, 182 p.
Research output: Thesis › Dissertation (TU Delft)

Open Access
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141 Downloads (Pure)

Cite this

Hashemi, M., Zhou, L., Shen, Y., Mehrpoo, M., & de Vreede, L. (2017). Highly Efficient and Linear Class-E CMOS Digital Power Amplifier Using a Compensated Marchand Balun and Circuit-Level Linearization Achieving 67% Peak DE and -40dBc ACLR without DPD. In 2017 IEEE MTT-S International Microwave Symposium (IMS) (pp. 2025 – 2028). IEEE. https://doi.org/10.1109/MWSYM.2017.8059066

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abstract = "A highly efficient and linear wideband digital polar CMOS class-E power amplifier (DPA) is presented. Using a compensated wideband Marchand balun with re-entrant coupled lines for the output matching network, more than 50% peak drain efficiency over 2.2-3GHz with 16-17dBm Pout are achieved. The linearity is significantly improved by nonlinearly sizing the DPA array along with overdrive-voltage control and concurrent multiphase RF clocking. The chip prototype is fabricated in 40nm bulk CMOS and the balun is fabricated on a two-layer PCB. Measured results show -40dBc for a 40MHz QAM signal at 2.6GHz without using any sort of DPD. The measured peak Pout, DE and PAE at 2.6GHz are 17.2dBm, 67% and 45% with VDD=0.7V.",

keywords = "Class-E, CMOS, digital PA, DPD-less, efficient, linear, wideband",

author = "Mohsen Hashemi and Lei Zhou and Yiyu Shen and Mohammadreza Mehrpoo and {de Vreede}, Leo",

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pages = "2025 – 2028",

booktitle = "2017 IEEE MTT-S International Microwave Symposium (IMS)",

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Hashemi, M, Zhou, L, Shen, Y, Mehrpoo, M & de Vreede, L 2017, Highly Efficient and Linear Class-E CMOS Digital Power Amplifier Using a Compensated Marchand Balun and Circuit-Level Linearization Achieving 67% Peak DE and -40dBc ACLR without DPD. in 2017 IEEE MTT-S International Microwave Symposium (IMS). IEEE, Piscataway, NJ, pp. 2025 – 2028, IEEE MTT-S International Microwave Symposium, IMS 2017, Honolulu, HI, United States, 4/06/17. https://doi.org/10.1109/MWSYM.2017.8059066

Highly Efficient and Linear Class-E CMOS Digital Power Amplifier Using a Compensated Marchand Balun and Circuit-Level Linearization Achieving 67% Peak DE and -40dBc ACLR without DPD. / Hashemi, Mohsen; Zhou, Lei; Shen, Yiyu et al.
2017 IEEE MTT-S International Microwave Symposium (IMS). Piscataway, NJ: IEEE, 2017. p. 2025 – 2028.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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T1 - Highly Efficient and Linear Class-E CMOS Digital Power Amplifier Using a Compensated Marchand Balun and Circuit-Level Linearization Achieving 67% Peak DE and -40dBc ACLR without DPD

AU - Hashemi, Mohsen

AU - Zhou, Lei

AU - Shen, Yiyu

AU - Mehrpoo, Mohammadreza

AU - de Vreede, Leo

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N2 - A highly efficient and linear wideband digital polar CMOS class-E power amplifier (DPA) is presented. Using a compensated wideband Marchand balun with re-entrant coupled lines for the output matching network, more than 50% peak drain efficiency over 2.2-3GHz with 16-17dBm Pout are achieved. The linearity is significantly improved by nonlinearly sizing the DPA array along with overdrive-voltage control and concurrent multiphase RF clocking. The chip prototype is fabricated in 40nm bulk CMOS and the balun is fabricated on a two-layer PCB. Measured results show -40dBc for a 40MHz QAM signal at 2.6GHz without using any sort of DPD. The measured peak Pout, DE and PAE at 2.6GHz are 17.2dBm, 67% and 45% with VDD=0.7V.

AB - A highly efficient and linear wideband digital polar CMOS class-E power amplifier (DPA) is presented. Using a compensated wideband Marchand balun with re-entrant coupled lines for the output matching network, more than 50% peak drain efficiency over 2.2-3GHz with 16-17dBm Pout are achieved. The linearity is significantly improved by nonlinearly sizing the DPA array along with overdrive-voltage control and concurrent multiphase RF clocking. The chip prototype is fabricated in 40nm bulk CMOS and the balun is fabricated on a two-layer PCB. Measured results show -40dBc for a 40MHz QAM signal at 2.6GHz without using any sort of DPD. The measured peak Pout, DE and PAE at 2.6GHz are 17.2dBm, 67% and 45% with VDD=0.7V.

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KW - CMOS

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ER -

Hashemi M, Zhou L, Shen Y, Mehrpoo M, de Vreede L. Highly Efficient and Linear Class-E CMOS Digital Power Amplifier Using a Compensated Marchand Balun and Circuit-Level Linearization Achieving 67% Peak DE and -40dBc ACLR without DPD. In 2017 IEEE MTT-S International Microwave Symposium (IMS). Piscataway, NJ: IEEE. 2017. p. 2025 – 2028 doi: 10.1109/MWSYM.2017.8059066

Highly Efficient and Linear Class-E CMOS Digital Power Amplifier Using a Compensated Marchand Balun and Circuit-Level Linearization Achieving 67% Peak DE and -40dBc ACLR without DPD

Abstract

Conference

Keywords

Access to Document

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Research output

Energy Efficient and Intrinsically Linear Digital Polar Transmitters

Cite this