Abstract
Adaptive voltage scaling (AVS) has been used widely to compensate for process, voltage, and temperature variations as well as power optimization of integrated circuits. The
current industrial state-of-the-art AVS approaches using Process Monitoring Boxes (PMBs) have shown several limitations such as huge characterization effort, which makes these approaches very expensive, and a low accuracy that results in extra margins, which consequently lead to yield loss and performance limitations.
To overcome those limitations, in this paper we propose an alternative solution using transition fault test patterns, which is able to eliminate the need for PMBs, while improving the accuracy of voltage estimation. The paper shows, using simulation of ISCAS’99 benchmarks with 28nm FD-SOI library, that AVS using transition fault testing (TF-based AVS) results in an error as low as 5.33%. The paper also shows that the PMB approach can only account for 85% of the uncertainty in voltage measurements, which results in power waste, while the TF-based approach can account for 99% of that uncertainty.
current industrial state-of-the-art AVS approaches using Process Monitoring Boxes (PMBs) have shown several limitations such as huge characterization effort, which makes these approaches very expensive, and a low accuracy that results in extra margins, which consequently lead to yield loss and performance limitations.
To overcome those limitations, in this paper we propose an alternative solution using transition fault test patterns, which is able to eliminate the need for PMBs, while improving the accuracy of voltage estimation. The paper shows, using simulation of ISCAS’99 benchmarks with 28nm FD-SOI library, that AVS using transition fault testing (TF-based AVS) results in an error as low as 5.33%. The paper also shows that the PMB approach can only account for 85% of the uncertainty in voltage measurements, which results in power waste, while the TF-based approach can account for 99% of that uncertainty.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) |
| Subtitle of host publication | Proceedings |
| Publisher | IEEE |
| Pages | 289-292 |
| Number of pages | 4 |
| ISBN (Electronic) | 978-3-9819263-0-9 |
| DOIs | |
| Publication status | Published - 2018 |
| Event | Design, Automation and Test in Europe: DATE 2018 - Dresden, Germany Duration: 19 Mar 2018 → 23 Mar 2018 |
Conference
| Conference | Design, Automation and Test in Europe |
|---|---|
| Country/Territory | Germany |
| City | Dresden |
| Period | 19/03/18 → 23/03/18 |