Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

M Taouil; S Hamdioui

doi:10.1109/ETS.2011.55

Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

20 Citations (Scopus)

Original language	English
Title of host publication	16th IEEE European Test Symposium
Editors	EJ Aas, L. Anghel
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE Society
Pages	45-50
Number of pages	6
ISBN (Print)	978-1-4577-0483-3
DOIs	https://doi.org/10.1109/ETS.2011.55
Publication status	Published - 2011
Event	ETS2011 - Piscataway, NJ, USA Duration: 23 May 2011 → 27 May 2011

Publication series

Name
Publisher	IEEE

Conference

Conference	ETS2011
Period	23/05/11 → 27/05/11

Keywords

Conf.proc. > 3 pag

Access to Document

10.1109/ETS.2011.55

Cite this

@inproceedings{502c702f0bce4bcbb0e20f77f3f43a5d,

title = "Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories",

keywords = "Conf.proc. > 3 pag",

author = "M Taouil and S Hamdioui",

year = "2011",

doi = "10.1109/ETS.2011.55",

language = "English",

isbn = "978-1-4577-0483-3",

publisher = "IEEE Society",

pages = "45--50",

editor = "EJ Aas and L. Anghel",

booktitle = "16th IEEE European Test Symposium",

note = "ETS2011 ; Conference date: 23-05-2011 Through 27-05-2011",

}

TY - GEN

T1 - Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

AU - Taouil, M

AU - Hamdioui, S

PY - 2011

Y1 - 2011

KW - Conf.proc. > 3 pag

U2 - 10.1109/ETS.2011.55

DO - 10.1109/ETS.2011.55

M3 - Conference contribution

SN - 978-1-4577-0483-3

SP - 45

EP - 50

BT - 16th IEEE European Test Symposium

A2 - Aas, EJ

A2 - Anghel, L.

PB - IEEE Society

CY - Piscataway, NJ, USA

T2 - ETS2011

Y2 - 23 May 2011 through 27 May 2011

ER -