Original language | English |
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Pages (from-to) | 1446-1450 |
Number of pages | 5 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 22 |
Issue number | 6 |
DOIs | |
Publication status | Published - 2014 |
Layout-based refined NPSF model for DRAM characterization and testing
Y Sfikas, YE Tsiatouhas, S Hamdioui
Research output: Contribution to journal › Article › Scientific › peer-review
4
Citations
(Scopus)