DOI

In this paper we introduce a novel error resilient memory architecture potentially applicable to a large range of memory technologies. In contrast with state of the art memory error correction schemes, which rely on (extended Hamming) Error Correcting Codes (ECC), we make use of Low Density Parity Check (LDPC) codes due to their close to the Shannon performance limit error correction capabilities. To allow for a cost-effective implementation we build our approach on top of a 3D memory organization which inherently fast and customizable wide-I/O vertical access allows for a smooth transfer of the required LDPC long code-words to/from an error correction dedicated die. To make the error correction process transparent to the memory users, e.g., processing cores, we propose an online memory scrubbing policy that performs the LDPC-based error detection and correction decoupled from the normal memory operation. For evaluation purposes we consider 3D memories protected by the proposed LDPC mechanism with various data width codes implementations. Simulation results indicate that our proposal clearly outperforms state of the art ECC schemes with fault tolerance improvements by a 4710× factor being obtained when compared to extended Hamming ECC. Furthermore, we evaluate instances of the proposed memory concept equipped with different LDPC codecs implemented on a commercial 40nm low-power CMOS technology and evaluate them on actual memory traces in terms of error correction capability, area, latency, and energy. Our results indicate that the LDPC protected memories offer substantially improved error correction capabilities, when compared to state of the art extended Hamming ECC, being able to assure clean runs for memory error rates α <; 3 × 10-2, which demonstrate that our proposal can potentially successfully protect system on a chip memory systems even in very harsh environmental conditions.
Original languageEnglish
Title of host publication2017 IEEE International Conference on Computer Design (ICCD)
PublisherIEEE
Pages265-268
Number of pages4
VolumePiscataway
ISBN (Electronic)978-1-5386-2254-4
ISBN (Print)978-1-5386-2255-1
DOIs
Publication statusPublished - 2017
Event2017 IEEE International Conference on Computer Design (ICCD): 35th IEEE International Conference on Computer Design - Boston, United States
Duration: 5 Nov 20178 Nov 2017

Conference

Conference2017 IEEE International Conference on Computer Design (ICCD)
CountryUnited States
CityBoston
Period5/11/178/11/17

    Research areas

  • 3.0, memory, error correction, ldpc, tsv, reliability

ID: 37380214