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LDPC-Based Adaptive Multi-Error Correction for 3D Memories. / Lefter, Mihai; Voicu, George; Marconi, Thomas; Savin, Valentin; Cotofana, Sorin.

2017 IEEE International Conference on Computer Design (ICCD). Vol. Piscataway IEEE, 2017. p. 265-268.

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Lefter, M, Voicu, G, Marconi, T, Savin, V & Cotofana, S 2017, LDPC-Based Adaptive Multi-Error Correction for 3D Memories. in 2017 IEEE International Conference on Computer Design (ICCD). vol. Piscataway, IEEE, pp. 265-268, 2017 IEEE International Conference on Computer Design (ICCD), Boston, United States, 5/11/17. https://doi.org/10.1109/ICCD.2017.47

APA

Lefter, M., Voicu, G., Marconi, T., Savin, V., & Cotofana, S. (2017). LDPC-Based Adaptive Multi-Error Correction for 3D Memories. In 2017 IEEE International Conference on Computer Design (ICCD) (Vol. Piscataway, pp. 265-268). IEEE. https://doi.org/10.1109/ICCD.2017.47

Vancouver

Lefter M, Voicu G, Marconi T, Savin V, Cotofana S. LDPC-Based Adaptive Multi-Error Correction for 3D Memories. In 2017 IEEE International Conference on Computer Design (ICCD). Vol. Piscataway. IEEE. 2017. p. 265-268 https://doi.org/10.1109/ICCD.2017.47

Author

Lefter, Mihai ; Voicu, George ; Marconi, Thomas ; Savin, Valentin ; Cotofana, Sorin. / LDPC-Based Adaptive Multi-Error Correction for 3D Memories. 2017 IEEE International Conference on Computer Design (ICCD). Vol. Piscataway IEEE, 2017. pp. 265-268

BibTeX

@inproceedings{20b919ae4f2a4182adaf5cc96218980d,
title = "LDPC-Based Adaptive Multi-Error Correction for 3D Memories",
abstract = "In this paper we introduce a novel error resilient memory architecture potentially applicable to a large range of memory technologies. In contrast with state of the art memory error correction schemes, which rely on (extended Hamming) Error Correcting Codes (ECC), we make use of Low Density Parity Check (LDPC) codes due to their close to the Shannon performance limit error correction capabilities. To allow for a cost-effective implementation we build our approach on top of a 3D memory organization which inherently fast and customizable wide-I/O vertical access allows for a smooth transfer of the required LDPC long code-words to/from an error correction dedicated die. To make the error correction process transparent to the memory users, e.g., processing cores, we propose an online memory scrubbing policy that performs the LDPC-based error detection and correction decoupled from the normal memory operation. For evaluation purposes we consider 3D memories protected by the proposed LDPC mechanism with various data width codes implementations. Simulation results indicate that our proposal clearly outperforms state of the art ECC schemes with fault tolerance improvements by a 4710× factor being obtained when compared to extended Hamming ECC. Furthermore, we evaluate instances of the proposed memory concept equipped with different LDPC codecs implemented on a commercial 40nm low-power CMOS technology and evaluate them on actual memory traces in terms of error correction capability, area, latency, and energy. Our results indicate that the LDPC protected memories offer substantially improved error correction capabilities, when compared to state of the art extended Hamming ECC, being able to assure clean runs for memory error rates α <; 3 × 10-2, which demonstrate that our proposal can potentially successfully protect system on a chip memory systems even in very harsh environmental conditions.",
keywords = "3.0, memory, error correction, ldpc, tsv, reliability",
author = "Mihai Lefter and George Voicu and Thomas Marconi and Valentin Savin and Sorin Cotofana",
year = "2017",
doi = "10.1109/ICCD.2017.47",
language = "English",
isbn = "978-1-5386-2255-1",
volume = "Piscataway",
pages = "265--268",
booktitle = "2017 IEEE International Conference on Computer Design (ICCD)",
publisher = "IEEE",
address = "United States",

}

RIS

TY - GEN

T1 - LDPC-Based Adaptive Multi-Error Correction for 3D Memories

AU - Lefter, Mihai

AU - Voicu, George

AU - Marconi, Thomas

AU - Savin, Valentin

AU - Cotofana, Sorin

PY - 2017

Y1 - 2017

N2 - In this paper we introduce a novel error resilient memory architecture potentially applicable to a large range of memory technologies. In contrast with state of the art memory error correction schemes, which rely on (extended Hamming) Error Correcting Codes (ECC), we make use of Low Density Parity Check (LDPC) codes due to their close to the Shannon performance limit error correction capabilities. To allow for a cost-effective implementation we build our approach on top of a 3D memory organization which inherently fast and customizable wide-I/O vertical access allows for a smooth transfer of the required LDPC long code-words to/from an error correction dedicated die. To make the error correction process transparent to the memory users, e.g., processing cores, we propose an online memory scrubbing policy that performs the LDPC-based error detection and correction decoupled from the normal memory operation. For evaluation purposes we consider 3D memories protected by the proposed LDPC mechanism with various data width codes implementations. Simulation results indicate that our proposal clearly outperforms state of the art ECC schemes with fault tolerance improvements by a 4710× factor being obtained when compared to extended Hamming ECC. Furthermore, we evaluate instances of the proposed memory concept equipped with different LDPC codecs implemented on a commercial 40nm low-power CMOS technology and evaluate them on actual memory traces in terms of error correction capability, area, latency, and energy. Our results indicate that the LDPC protected memories offer substantially improved error correction capabilities, when compared to state of the art extended Hamming ECC, being able to assure clean runs for memory error rates α <; 3 × 10-2, which demonstrate that our proposal can potentially successfully protect system on a chip memory systems even in very harsh environmental conditions.

AB - In this paper we introduce a novel error resilient memory architecture potentially applicable to a large range of memory technologies. In contrast with state of the art memory error correction schemes, which rely on (extended Hamming) Error Correcting Codes (ECC), we make use of Low Density Parity Check (LDPC) codes due to their close to the Shannon performance limit error correction capabilities. To allow for a cost-effective implementation we build our approach on top of a 3D memory organization which inherently fast and customizable wide-I/O vertical access allows for a smooth transfer of the required LDPC long code-words to/from an error correction dedicated die. To make the error correction process transparent to the memory users, e.g., processing cores, we propose an online memory scrubbing policy that performs the LDPC-based error detection and correction decoupled from the normal memory operation. For evaluation purposes we consider 3D memories protected by the proposed LDPC mechanism with various data width codes implementations. Simulation results indicate that our proposal clearly outperforms state of the art ECC schemes with fault tolerance improvements by a 4710× factor being obtained when compared to extended Hamming ECC. Furthermore, we evaluate instances of the proposed memory concept equipped with different LDPC codecs implemented on a commercial 40nm low-power CMOS technology and evaluate them on actual memory traces in terms of error correction capability, area, latency, and energy. Our results indicate that the LDPC protected memories offer substantially improved error correction capabilities, when compared to state of the art extended Hamming ECC, being able to assure clean runs for memory error rates α <; 3 × 10-2, which demonstrate that our proposal can potentially successfully protect system on a chip memory systems even in very harsh environmental conditions.

KW - 3.0

KW - memory

KW - error correction

KW - ldpc

KW - tsv

KW - reliability

U2 - 10.1109/ICCD.2017.47

DO - 10.1109/ICCD.2017.47

M3 - Conference contribution

SN - 978-1-5386-2255-1

VL - Piscataway

SP - 265

EP - 268

BT - 2017 IEEE International Conference on Computer Design (ICCD)

PB - IEEE

ER -

ID: 37380214