@inproceedings{bb25d339e53747c4a1bfd8156b0bc286,
title = "Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/Threshold-logic approach",
keywords = "conference contrib. refereed, Conf.proc. > 3 pag",
author = "P Celinski and S Al-Sarawi and D Abbott and SD Cotofana and S Vassiliadis",
year = "2004",
language = "Undefined/Unknown",
isbn = "0-7695-2097-9",
publisher = "IEEE ",
pages = "127--132",
editor = "A Smailagic and M Bayoumi",
booktitle = "Proceedings IEEE Computer Society annual symposium on VLSI; Emerging trends in VLSI systems design",
address = "United States",
note = "IEEE Computer Society annual symposium on VLSI; Emerging trends in VLSI systems design, Lafayette, USA ; Conference date: 19-02-2004 Through 20-02-2004",
}