The 3D stacked hybrid memory relies on a hysteretic Nano-Electro-Mechanical Field Effect Transistor (NEMFET) inverter to store data, and on adjacent CMOS based logic to allow for read/write operations, and data preservation. In this paper we assess the feasibility of a hybrid memory cell, and explore the design space of 3D stacked hybrid dual-port memory arrays which combine the appealing NEMFET properties, i.e., ultra-low leakage currents and abrupt switching, with the CMOS technology versatility. In the evaluation we performed a comparison in terms of footprint, access time, and energy, against state of the art CMOS dual-ports memories, considering small and large size memory arrays (8-Kbytes up to 128-Kbytes) implemented in various technology nodes. The 3D NEMFETCMOS hybrid dual-port memory is on the average 25% smaller and 8% and 95% larger in terms of footprint when compared to 90nm, 65nm and 45nm CMOS implementations, respectively. The write access time is approximately 2 higher, as it is dominated by the mechanical movement of the NEMFET’s suspended gate, while the read access time is about 12% lower, when compared with 45nm CMOS counterparts. For small size memories our proposal results in at least 15% and 23% energy reductions for 100% and 50% data transition probability, respectively. For large size memories an energy reduction of about 40% was obtained, as in this case the static energy is predominant.
Original languageEnglish
Pages (from-to)184-199
Number of pages16
JournalIEEE Transactions on Emerging Topics in Computing
Volume6
Issue number2
DOIs
Publication statusPublished - 2018

    Research areas

  • NEMFET, emerging memories, 3D-Stacked, TSV, hybrid integrated circuits, CMOS memory circuitS, power consumption

ID: 10408218