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Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory. / Enachescu, Marius; Lefter, Mihai; Voicu, George; Cotofana, Sorin.

In: IEEE Transactions on Emerging Topics in Computing, Vol. 6, No. 2, 2018, p. 184-199.

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Enachescu, Marius ; Lefter, Mihai ; Voicu, George ; Cotofana, Sorin. / Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory. In: IEEE Transactions on Emerging Topics in Computing. 2018 ; Vol. 6, No. 2. pp. 184-199.

BibTeX

@article{84fc4e6097244791b00ab927df3f26f5,
title = "Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory",
abstract = "The 3D stacked hybrid memory relies on a hysteretic Nano-Electro-Mechanical Field Effect Transistor (NEMFET) inverter to store data, and on adjacent CMOS based logic to allow for read/write operations, and data preservation. In this paper we assess the feasibility of a hybrid memory cell, and explore the design space of 3D stacked hybrid dual-port memory arrays which combine the appealing NEMFET properties, i.e., ultra-low leakage currents and abrupt switching, with the CMOS technology versatility. In the evaluation we performed a comparison in terms of footprint, access time, and energy, against state of the art CMOS dual-ports memories, considering small and large size memory arrays (8-Kbytes up to 128-Kbytes) implemented in various technology nodes. The 3D NEMFETCMOS hybrid dual-port memory is on the average 25{\%} smaller and 8{\%} and 95{\%} larger in terms of footprint when compared to 90nm, 65nm and 45nm CMOS implementations, respectively. The write access time is approximately 2 higher, as it is dominated by the mechanical movement of the NEMFET’s suspended gate, while the read access time is about 12{\%} lower, when compared with 45nm CMOS counterparts. For small size memories our proposal results in at least 15{\%} and 23{\%} energy reductions for 100{\%} and 50{\%} data transition probability, respectively. For large size memories an energy reduction of about 40{\%} was obtained, as in this case the static energy is predominant.",
keywords = "NEMFET, emerging memories, 3D-Stacked, TSV, hybrid integrated circuits, CMOS memory circuitS, power consumption",
author = "Marius Enachescu and Mihai Lefter and George Voicu and Sorin Cotofana",
year = "2018",
doi = "10.1109/TETC.2016.2588725",
language = "English",
volume = "6",
pages = "184--199",
journal = "IEEE Transactions on Emerging Topics in Computing",
issn = "2168-6750",
publisher = "IEEE Computer Society",
number = "2",

}

RIS

TY - JOUR

T1 - Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory

AU - Enachescu, Marius

AU - Lefter, Mihai

AU - Voicu, George

AU - Cotofana, Sorin

PY - 2018

Y1 - 2018

N2 - The 3D stacked hybrid memory relies on a hysteretic Nano-Electro-Mechanical Field Effect Transistor (NEMFET) inverter to store data, and on adjacent CMOS based logic to allow for read/write operations, and data preservation. In this paper we assess the feasibility of a hybrid memory cell, and explore the design space of 3D stacked hybrid dual-port memory arrays which combine the appealing NEMFET properties, i.e., ultra-low leakage currents and abrupt switching, with the CMOS technology versatility. In the evaluation we performed a comparison in terms of footprint, access time, and energy, against state of the art CMOS dual-ports memories, considering small and large size memory arrays (8-Kbytes up to 128-Kbytes) implemented in various technology nodes. The 3D NEMFETCMOS hybrid dual-port memory is on the average 25% smaller and 8% and 95% larger in terms of footprint when compared to 90nm, 65nm and 45nm CMOS implementations, respectively. The write access time is approximately 2 higher, as it is dominated by the mechanical movement of the NEMFET’s suspended gate, while the read access time is about 12% lower, when compared with 45nm CMOS counterparts. For small size memories our proposal results in at least 15% and 23% energy reductions for 100% and 50% data transition probability, respectively. For large size memories an energy reduction of about 40% was obtained, as in this case the static energy is predominant.

AB - The 3D stacked hybrid memory relies on a hysteretic Nano-Electro-Mechanical Field Effect Transistor (NEMFET) inverter to store data, and on adjacent CMOS based logic to allow for read/write operations, and data preservation. In this paper we assess the feasibility of a hybrid memory cell, and explore the design space of 3D stacked hybrid dual-port memory arrays which combine the appealing NEMFET properties, i.e., ultra-low leakage currents and abrupt switching, with the CMOS technology versatility. In the evaluation we performed a comparison in terms of footprint, access time, and energy, against state of the art CMOS dual-ports memories, considering small and large size memory arrays (8-Kbytes up to 128-Kbytes) implemented in various technology nodes. The 3D NEMFETCMOS hybrid dual-port memory is on the average 25% smaller and 8% and 95% larger in terms of footprint when compared to 90nm, 65nm and 45nm CMOS implementations, respectively. The write access time is approximately 2 higher, as it is dominated by the mechanical movement of the NEMFET’s suspended gate, while the read access time is about 12% lower, when compared with 45nm CMOS counterparts. For small size memories our proposal results in at least 15% and 23% energy reductions for 100% and 50% data transition probability, respectively. For large size memories an energy reduction of about 40% was obtained, as in this case the static energy is predominant.

KW - NEMFET

KW - emerging memories

KW - 3D-Stacked

KW - TSV

KW - hybrid integrated circuits

KW - CMOS memory circuitS

KW - power consumption

U2 - 10.1109/TETC.2016.2588725

DO - 10.1109/TETC.2016.2588725

M3 - Article

VL - 6

SP - 184

EP - 199

JO - IEEE Transactions on Emerging Topics in Computing

T2 - IEEE Transactions on Emerging Topics in Computing

JF - IEEE Transactions on Emerging Topics in Computing

SN - 2168-6750

IS - 2

ER -

ID: 10408218