Standard

Memristive Device Based Circuits for Computation-in-Memory Architectures. / Lebdeh, Muath Abu; Reinsalu, Uljana; Du Nguyen, Hoang Anh; Wong, Stephan; Hamdioui, Said.

2019 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway, NJ : IEEE, 2019. p. 1-5 8702542.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Harvard

Lebdeh, MA, Reinsalu, U, Du Nguyen, HA, Wong, S & Hamdioui, S 2019, Memristive Device Based Circuits for Computation-in-Memory Architectures. in 2019 IEEE International Symposium on Circuits and Systems (ISCAS)., 8702542, IEEE, Piscataway, NJ, pp. 1-5, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, 26/05/19. https://doi.org/10.1109/ISCAS.2019.8702542

APA

Lebdeh, M. A., Reinsalu, U., Du Nguyen, H. A., Wong, S., & Hamdioui, S. (2019). Memristive Device Based Circuits for Computation-in-Memory Architectures. In 2019 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1-5). [8702542] IEEE. https://doi.org/10.1109/ISCAS.2019.8702542

Vancouver

Lebdeh MA, Reinsalu U, Du Nguyen HA, Wong S, Hamdioui S. Memristive Device Based Circuits for Computation-in-Memory Architectures. In 2019 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway, NJ: IEEE. 2019. p. 1-5. 8702542 https://doi.org/10.1109/ISCAS.2019.8702542

Author

Lebdeh, Muath Abu ; Reinsalu, Uljana ; Du Nguyen, Hoang Anh ; Wong, Stephan ; Hamdioui, Said. / Memristive Device Based Circuits for Computation-in-Memory Architectures. 2019 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway, NJ : IEEE, 2019. pp. 1-5

BibTeX

@inproceedings{2a2fb34b8c3a41f1b13f7c6a909747dd,
title = "Memristive Device Based Circuits for Computation-in-Memory Architectures",
abstract = "Emerging computing applications (such as big-data and Internet-of-things) are extremely demanding in terms of storage, energy and computational efficiency, while today{\textquoteright}s architectures and device technologies are facing major challenges making them incapable to meet these demands. Computation-in-Memory (CIM) architecture based on memristive devices is one of the alternative computing architectures being explored to address these limitations. Enabling such architectures relies on the development of efficient memristive circuits being able to perform logic and arithmetic operations within the non-volatile memory core. This paper addresses memristive circuit designs for CIM architectures. It gives a complete overview of all designs, both for logic as well as arithmetic operations, and presents the most popular designs in details. In addition, it analyzes and classifies them, shows how they result in different CIM flavours and how these architectures distinguish themselves from traditional ones. The paper also presents different potential applications that could significantly benefit from CIM architectures, based on their kernel that could be accelerated. ",
author = "Lebdeh, {Muath Abu} and Uljana Reinsalu and {Du Nguyen}, {Hoang Anh} and Stephan Wong and Said Hamdioui",
note = "Accepted author manuscript; 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 ; Conference date: 26-05-2019 Through 29-05-2019",
year = "2019",
month = may,
day = "1",
doi = "10.1109/ISCAS.2019.8702542",
language = "English",
isbn = "978-1-7281-0398-3",
pages = "1--5",
booktitle = "2019 IEEE International Symposium on Circuits and Systems (ISCAS)",
publisher = "IEEE",
address = "United States",

}

RIS

TY - GEN

T1 - Memristive Device Based Circuits for Computation-in-Memory Architectures

AU - Lebdeh, Muath Abu

AU - Reinsalu, Uljana

AU - Du Nguyen, Hoang Anh

AU - Wong, Stephan

AU - Hamdioui, Said

N1 - Accepted author manuscript

PY - 2019/5/1

Y1 - 2019/5/1

N2 - Emerging computing applications (such as big-data and Internet-of-things) are extremely demanding in terms of storage, energy and computational efficiency, while today’s architectures and device technologies are facing major challenges making them incapable to meet these demands. Computation-in-Memory (CIM) architecture based on memristive devices is one of the alternative computing architectures being explored to address these limitations. Enabling such architectures relies on the development of efficient memristive circuits being able to perform logic and arithmetic operations within the non-volatile memory core. This paper addresses memristive circuit designs for CIM architectures. It gives a complete overview of all designs, both for logic as well as arithmetic operations, and presents the most popular designs in details. In addition, it analyzes and classifies them, shows how they result in different CIM flavours and how these architectures distinguish themselves from traditional ones. The paper also presents different potential applications that could significantly benefit from CIM architectures, based on their kernel that could be accelerated.

AB - Emerging computing applications (such as big-data and Internet-of-things) are extremely demanding in terms of storage, energy and computational efficiency, while today’s architectures and device technologies are facing major challenges making them incapable to meet these demands. Computation-in-Memory (CIM) architecture based on memristive devices is one of the alternative computing architectures being explored to address these limitations. Enabling such architectures relies on the development of efficient memristive circuits being able to perform logic and arithmetic operations within the non-volatile memory core. This paper addresses memristive circuit designs for CIM architectures. It gives a complete overview of all designs, both for logic as well as arithmetic operations, and presents the most popular designs in details. In addition, it analyzes and classifies them, shows how they result in different CIM flavours and how these architectures distinguish themselves from traditional ones. The paper also presents different potential applications that could significantly benefit from CIM architectures, based on their kernel that could be accelerated.

UR - http://www.scopus.com/inward/record.url?scp=85066016527&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2019.8702542

DO - 10.1109/ISCAS.2019.8702542

M3 - Conference contribution

SN - 978-1-7281-0398-3

SP - 1

EP - 5

BT - 2019 IEEE International Symposium on Circuits and Systems (ISCAS)

PB - IEEE

CY - Piscataway, NJ

T2 - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019

Y2 - 26 May 2019 through 29 May 2019

ER -

ID: 53706812