Memory designs typically contain design margins to compensate for aging. As aging impact becomes more severe with technology scaling, it is crucial to accurately predict such impact to prevent overestimation or underestimation of the margins. This paper proposes a methodology to accurately and efficiently analyze the impact of aging on the memory's digital logic (e.g., timing circuit and address decoder) while considering realistic workloads extracted from applications. To demonstrate the superiority of the methodology, we analyzed the degradation of the L1 data and instruction caches for an ARM v8-a processor using both our methodology as well as the state-of-the-art methods. The results show that the existing methods may significantly over-or underestimate the impact (e.g., the decoder margin up to 221% and the access time up to 20%) as compared with the proposed scheme. In addition, the results show that in general the instruction cache has the highest degradation. For example, its access time degrades up to 9% and its decoder margin up to 44%.

Original languageEnglish
Title of host publication2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Subtitle of host publicationProceedings
PublisherIEEE
Pages162-167
Number of pages6
ISBN (Electronic)978-3-9819263-2-3
ISBN (Print)978-1-7281-0331-0
DOIs
Publication statusPublished - 2019
EventDATE 2019 : Design, Automation and Test in Europe Conference and Exhibition - Florence, Italy
Duration: 25 Mar 201929 Mar 2019
Conference number: 22nd

Conference

ConferenceDATE 2019
CountryItaly
CityFlorence
Period25/03/1929/03/19

    Research areas

  • Address Decoder, Aging, Memory, Timing

ID: 54216908