To compensate for time-zero (due to process variation) and time-dependent (due to e.g. Bias Temperature Instability (BTI)) variability, designers usually add design margins. Due to technology scaling, these variabilities become worse, leading to the need for bigger design margins. Typically, only worst-case scenarios are considered, which will not present the actual workload of the targeted application. Alternatively, mitigation schemes can be used to counteract the variability. This paper presents a run-time design-for-reliability scheme for memory Sense Amplifiers (SAs); SAs are an integral part of any memory system and are very critical for high performance. The proposed scheme mitigates the impact of time-dependent variability due to aging by using an on-line control circuit to create a balanced workload. The simulation results show that the proposed scheme can reduce the most critical figures-of-merit, namely the offset voltage shift and the sensing delay of the SA with up to ~40% and ~10%, respectively, depending on the stress conditions (temperature, voltage, workload).
Original languageEnglish
Title of host publicationProceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)
PublisherIEEE
Pages858-863
Number of pages6
ISBN (Electronic)978-3-9815370-8-6
ISBN (Print)978-1-5090-5826-6
DOIs
Publication statusPublished - 2017
EventDesign, Automation and Test in Europe: DATE 17 - SwissTech Convention Centre, Lausanne, Switzerland
Duration: 27 Mar 201731 Mar 2017

Conference

ConferenceDesign, Automation and Test in Europe
CountrySwitzerland
CityLausanne
Period27/03/1731/03/17

    Research areas

  • Mitigation, Offset voltage, zero-time variability, run-time variability, SRAM sense amplifier, sensing delay

ID: 37689206