Modular time-of-flight image sensor for light detection and ranging: A digital approach to LIDAR

Constant increase in data processing efficiency has enabled, among many other things, the intensive use of depth mapping technologies. Consumer applications, such as gaming, augmented and virtual realities (AR/VR), and other human-machine interfaces, are typically based on intensive image processing, either by triangulation and/or structured light, which has limitations on speed, resolution, range, and robustness to background noise. On the other hand, TOF depth sensing has been investigated in the academic and industrial engineering communities for several years, as an alternative to solve such restrictions, and few products are emerging. Direct time-of-flight (dTOF), specifically, requires more elaborate detectors and data processing, but it has the potential of reaching much longer distances at higher speed and accuracy, with the advantage of being robust to high background noise, making it suitable for space, automotive and consumer applications. One known drawback of dTOF, however, is data volume. For instance, automotive applications require over 100m range, only few centimeters accuracy, and multiple measurements for a reasonable precision, which produce data rates that can reach tens or even hundreds of Gbps, in large sensors, thus setting processing constraints to even very efficient GPUs, as well as chip readout capability. It is essential to provide as much on-chip processing as possible, in order to reduce data throughput, thus reducing power consumption and speeding up processing time. Some architectures have been proposed attempting to solve this problem, but the required memory renders them only feasible for an SiPM, single-pixel approach. Another known issue with light detection and ranging (LiDAR) is regarding the interference of multiple systems on each other. A software-based approach has been implemented, but requiring intensive post-processing resources. In this thesis, a novel approach for on-chip processing is proposed. With the use of cutting-edge 3D-stacking technologies, more flexibility and computational power can be spent on the chip, while not compromising fill factor. A novel proposal for dealing with external interferes is introduced, as well as novel phase/frequency locking solution at the sensor level, as a reference for timing measurements.