Standard

Multilayer VLSI layout for interconnection networks. / Yeh, CH; Varvarigos, EA; Parhami, B.

ICPP 2000 proceedings. ed. / DJ Lilja. Los Alamitos : IEEE, 2000. p. 33-40.

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

Harvard

Yeh, CH, Varvarigos, EA & Parhami, B 2000, Multilayer VLSI layout for interconnection networks. in DJ Lilja (ed.), ICPP 2000 proceedings. IEEE, Los Alamitos, pp. 33-40, 2000 International Conference on Parallel Processing, Toronto, 21/08/00.

APA

Yeh, CH., Varvarigos, EA., & Parhami, B. (2000). Multilayer VLSI layout for interconnection networks. In DJ Lilja (Ed.), ICPP 2000 proceedings (pp. 33-40). Los Alamitos: IEEE.

Vancouver

Yeh CH, Varvarigos EA, Parhami B. Multilayer VLSI layout for interconnection networks. In DJ Lilja, editor, ICPP 2000 proceedings. Los Alamitos: IEEE. 2000. p. 33-40

Author

Yeh, CH ; Varvarigos, EA ; Parhami, B. / Multilayer VLSI layout for interconnection networks. ICPP 2000 proceedings. editor / DJ Lilja. Los Alamitos : IEEE, 2000. pp. 33-40

BibTeX

@inproceedings{71d5d738bfd543889fee0d047003f53f,
title = "Multilayer VLSI layout for interconnection networks",
keywords = "ZX Int.klas.verslagjaar < 2002",
author = "CH Yeh and EA Varvarigos and B Parhami",
year = "2000",
language = "Undefined/Unknown",
isbn = "0-7695-0768-9",
publisher = "IEEE",
pages = "33--40",
editor = "{DJ Lilja}",
booktitle = "ICPP 2000 proceedings",
address = "United States",

}

RIS

TY - GEN

T1 - Multilayer VLSI layout for interconnection networks

AU - Yeh, CH

AU - Varvarigos, EA

AU - Parhami, B

PY - 2000

Y1 - 2000

KW - ZX Int.klas.verslagjaar < 2002

M3 - Conference contribution

SN - 0-7695-0768-9

SP - 33

EP - 40

BT - ICPP 2000 proceedings

A2 - DJ Lilja, null

PB - IEEE

CY - Los Alamitos

ER -

ID: 3182303