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Multiple contexts in a multi-ported VLIW register file implementation. / Hoozemans, Joost; Johansen, Jens; Van Straten, Jeroen; Brandon, Anthony; Wong, Stephan.

2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7393329.

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Hoozemans, J, Johansen, J, Van Straten, J, Brandon, A & Wong, S 2015, Multiple contexts in a multi-ported VLIW register file implementation. in 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015., 7393329, Institute of Electrical and Electronics Engineers Inc., International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, Riviera Maya, Mexico, 7/12/15. https://doi.org/10.1109/ReConFig.2015.7393329

APA

Hoozemans, J., Johansen, J., Van Straten, J., Brandon, A., & Wong, S. (2015). Multiple contexts in a multi-ported VLIW register file implementation. In 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015 [7393329] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ReConFig.2015.7393329

Vancouver

Hoozemans J, Johansen J, Van Straten J, Brandon A, Wong S. Multiple contexts in a multi-ported VLIW register file implementation. In 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7393329 https://doi.org/10.1109/ReConFig.2015.7393329

Author

Hoozemans, Joost ; Johansen, Jens ; Van Straten, Jeroen ; Brandon, Anthony ; Wong, Stephan. / Multiple contexts in a multi-ported VLIW register file implementation. 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers Inc., 2015.

BibTeX

@inproceedings{0f12e3f1874d499ea936d288ab434e86,
title = "Multiple contexts in a multi-ported VLIW register file implementation",
abstract = "The register file is an expensive component in the design of any processor, especially, when considering the additional ports that are needed to support multiple datapaths within a wide-issue VLIW processor. In a recent work, these additional resources were used to dynamically reconfigure the register file to support a dynamically reconfigurable VLIW core. The design can be perceived as a single 8-issue, two 4-issue, or four 2-issue VLIW cores. Consequently, the multi-ported design can operate in different modes, namely as one, two, or four register files, respectively, corresponding to the active number of cores. The implementation of the register file design on FPGAs using Block RAMs still results in unused resources due to the coarseness of the Block RAMs. In this paper, we propose to re-purpose these unused BRAM resources to additionally support multiple contexts next to earliermentioned modes. In this manner, the 8-issue, 4-issue, and 2- issue cores have access to 4, 2, and 1 contexts, respectively. Consequently, we can avoid saving and restoring of the task states in a multi-task environment, turning context switching from a traditionally time-consuming event to an almost instantaneous event. The advantage of this is the reduction of interrupt latency and task switching latency, which are important in real-time and embedded systems. Our results show that our technique can improve interrupt latency by a factor of 17.4x compared to using a software register spill routine, depending on the behavior of the memory system. Likewise, the task switching time can be improved by 6.7x.",
author = "Joost Hoozemans and Jens Johansen and {Van Straten}, Jeroen and Anthony Brandon and Stephan Wong",
year = "2015",
month = "12",
day = "7",
doi = "10.1109/ReConFig.2015.7393329",
language = "English",
booktitle = "2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

RIS

TY - GEN

T1 - Multiple contexts in a multi-ported VLIW register file implementation

AU - Hoozemans, Joost

AU - Johansen, Jens

AU - Van Straten, Jeroen

AU - Brandon, Anthony

AU - Wong, Stephan

PY - 2015/12/7

Y1 - 2015/12/7

N2 - The register file is an expensive component in the design of any processor, especially, when considering the additional ports that are needed to support multiple datapaths within a wide-issue VLIW processor. In a recent work, these additional resources were used to dynamically reconfigure the register file to support a dynamically reconfigurable VLIW core. The design can be perceived as a single 8-issue, two 4-issue, or four 2-issue VLIW cores. Consequently, the multi-ported design can operate in different modes, namely as one, two, or four register files, respectively, corresponding to the active number of cores. The implementation of the register file design on FPGAs using Block RAMs still results in unused resources due to the coarseness of the Block RAMs. In this paper, we propose to re-purpose these unused BRAM resources to additionally support multiple contexts next to earliermentioned modes. In this manner, the 8-issue, 4-issue, and 2- issue cores have access to 4, 2, and 1 contexts, respectively. Consequently, we can avoid saving and restoring of the task states in a multi-task environment, turning context switching from a traditionally time-consuming event to an almost instantaneous event. The advantage of this is the reduction of interrupt latency and task switching latency, which are important in real-time and embedded systems. Our results show that our technique can improve interrupt latency by a factor of 17.4x compared to using a software register spill routine, depending on the behavior of the memory system. Likewise, the task switching time can be improved by 6.7x.

AB - The register file is an expensive component in the design of any processor, especially, when considering the additional ports that are needed to support multiple datapaths within a wide-issue VLIW processor. In a recent work, these additional resources were used to dynamically reconfigure the register file to support a dynamically reconfigurable VLIW core. The design can be perceived as a single 8-issue, two 4-issue, or four 2-issue VLIW cores. Consequently, the multi-ported design can operate in different modes, namely as one, two, or four register files, respectively, corresponding to the active number of cores. The implementation of the register file design on FPGAs using Block RAMs still results in unused resources due to the coarseness of the Block RAMs. In this paper, we propose to re-purpose these unused BRAM resources to additionally support multiple contexts next to earliermentioned modes. In this manner, the 8-issue, 4-issue, and 2- issue cores have access to 4, 2, and 1 contexts, respectively. Consequently, we can avoid saving and restoring of the task states in a multi-task environment, turning context switching from a traditionally time-consuming event to an almost instantaneous event. The advantage of this is the reduction of interrupt latency and task switching latency, which are important in real-time and embedded systems. Our results show that our technique can improve interrupt latency by a factor of 17.4x compared to using a software register spill routine, depending on the behavior of the memory system. Likewise, the task switching time can be improved by 6.7x.

UR - http://www.scopus.com/inward/record.url?scp=84964341289&partnerID=8YFLogxK

U2 - 10.1109/ReConFig.2015.7393329

DO - 10.1109/ReConFig.2015.7393329

M3 - Conference contribution

BT - 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

ID: 11720752