The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK.

Original languageEnglish
Title of host publication2017 47th European Solid-State Device Research Conference, ESSDERC 2017
EditorsJo Boeck, De, Georges Gielen
PublisherEditions Frontieres
Number of pages4
ISBN (Electronic)978-150905978-2
Publication statusPublished - 12 Oct 2017
EventESSDERC-ESSCIRC 2017: 47th European Solid-State Device Research Conference - 43rd European Solid-State Circuits Conference - Leuven, Belgium
Duration: 11 Sep 201714 Sep 2017


ConferenceESSDERC-ESSCIRC 2017
Internet address

ID: 34526544