TY - JOUR
T1 - NBTI stress delay sensitivity analysis of reliability enhanced Schmitt trigger based circuits
AU - Shah, Ambika Prasad
AU - Vishvakarma, Santosh Kumar
AU - Cotofana, Sorin
PY - 2019/11/1
Y1 - 2019/11/1
N2 - Negative Bias Temperature Instability (NBTI) in PMOS transistors results in increased transistor threshold voltage, is considered the major contributor to circuit performance degradation and to alleviate its effect appropriate design and lifetime measures are required. In this paper, we concentrate on a design-time solution, i.e., the replacement of CMOS inverters by more reliable counterparts, i.e., Schmitt Trigger (ST) and NMOS only Schmitt Trigger with Voltage Booster (NST-VB). We first compare the three candidates implemented in 32 nm CMOS technology concerning delay variation. Our results indicate that, after three years of NBTI stress, NST-VB exhibits an almost negligible delay shift of 0.47%, while ST and CMOS inverter experience a delay shift of 7.2% and 5.32%, respectively. Subsequently, we extend the scope and assume the ISCAS'89 s27 circuit as a discussion vehicle. Our evaluations indicate that after 3-year stress time, the critical path delay of the s27 CMOS, ST, and NST-VB based implementations increases by 105.1 ps, 185.2 ps, and 94.2 ps, respectively. To put things into a better perspective, we introduce the Inverse Power Area Reliability Product (IPARP) as compound reliability metric. Our analysis indicates that the normalized IPARP values for ST and NST-VB implementations are 0.062 and 1.903, respectively, compared to CMOS implementation.
AB - Negative Bias Temperature Instability (NBTI) in PMOS transistors results in increased transistor threshold voltage, is considered the major contributor to circuit performance degradation and to alleviate its effect appropriate design and lifetime measures are required. In this paper, we concentrate on a design-time solution, i.e., the replacement of CMOS inverters by more reliable counterparts, i.e., Schmitt Trigger (ST) and NMOS only Schmitt Trigger with Voltage Booster (NST-VB). We first compare the three candidates implemented in 32 nm CMOS technology concerning delay variation. Our results indicate that, after three years of NBTI stress, NST-VB exhibits an almost negligible delay shift of 0.47%, while ST and CMOS inverter experience a delay shift of 7.2% and 5.32%, respectively. Subsequently, we extend the scope and assume the ISCAS'89 s27 circuit as a discussion vehicle. Our evaluations indicate that after 3-year stress time, the critical path delay of the s27 CMOS, ST, and NST-VB based implementations increases by 105.1 ps, 185.2 ps, and 94.2 ps, respectively. To put things into a better perspective, we introduce the Inverse Power Area Reliability Product (IPARP) as compound reliability metric. Our analysis indicates that the normalized IPARP values for ST and NST-VB implementations are 0.062 and 1.903, respectively, compared to CMOS implementation.
KW - Design for reliability
KW - ISCAS'89 s27 benchmark suite
KW - NBTI
KW - Reliability
KW - Schmitt trigger
KW - Threshold voltage degradation
UR - http://www.scopus.com/inward/record.url?scp=85068971323&partnerID=8YFLogxK
U2 - 10.1016/j.microrel.2019.06.083
DO - 10.1016/j.microrel.2019.06.083
M3 - Article
AN - SCOPUS:85068971323
SN - 0026-2714
VL - 102
SP - 1
EP - 8
JO - Microelectronics Reliability
JF - Microelectronics Reliability
M1 - 113391
ER -