DOI

This paper analyzes the contribution of caches to failures at processor level due to soft errors. In order to do this, approximated methodologies to estimate the percentage of the total Sensitive Area (SA) of a processor for each unit during early design exploration are proposed. Then, to identify the most vulnerable units, a metric called Relative Soft Error Vulnerability (RSEV) is defined. The analysis shows that caches are the most vulnerable units of state-of-the-art processors and that, even when considering higher-frequency and more complex pipelines representative of next-generation processors for space applications, the final in-orbit failure rate is dominated by failures caused by upsets in cache arrays. Even when protecting memory arrays with information redundancy, the large fraction of upsets occurring in caches is potentially the biggest threat to processor availability and reliability, especially if errors are modelled with invalid assumptions and are not properly handled when detected.

Original languageEnglish
Title of host publication2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)9781728122601
DOIs
Publication statusPublished - 1 Oct 2019
Event32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 - Noordwijk, Netherlands
Duration: 2 Oct 20194 Oct 2019

Conference

Conference32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019
CountryNetherlands
CityNoordwijk
Period2/10/194/10/19

ID: 66542880