• Mansoureh Labafniya
  • Stjepan Picek
  • Shahram Etemadi Borujeni
  • Nele Mentens

Evolvable hardware (EH) architectures are capable of changing their configuration and behavior dynamically based on inputs from the environment. In this paper, we investigate the feasibility of using EH to prevent Hardware Trojan Horses (HTHs) from being inserted, activated, or propagated in a digital electronic chip. HTHs are malicious hardware components that intend to leak secret information or cause malfunctioning at run-time in the chip in which they are integrated. We hypothesize that EH can detect internal circuit errors at run-time and reconfigure to a state in which the errors are no longer present. We implement a Virtual Reconfigurable Circuit (VRC) on a Field-Programmable Gate Array (FPGA) that autonomously and periodically reconfigures itself based on an Evolutionary Algorithm (EA). New VRC configurations are generated with an on-chip EA engine. We show that the presented approach is applicable in a scenario in which (1) the HTH-critical areas in the circuit are known in advance, and (2) the VRC is a purely combinatorial circuit, as opposed to the on-chip memory holding the golden reference, which requires one or more cycles to be read/written. We compare two different approaches for protecting the system against HTHs: Genetic Programming (GP) and Cartesian Genetic Programming (CGP). The paper reports on experiments on four benchmark circuits and gives an overview of both the limitations and the added value of the presented approaches.

Original languageEnglish
Article number106247
Number of pages11
JournalApplied Soft Computing Journal
Volume91
DOIs
Publication statusPublished - 1 Jun 2020

    Research areas

  • Evolvable Hardware (EH), Field-Programmable Gate Array (FPGA), Hardware security, Hardware Trojan Horse (HTH), Virtual Reconfigurable Circuit (VRC)

ID: 72096721