As today's CMOS technology is scaling down to its physical limits, it suffers from major challenges such as increased leakage power and reduced reliability. Novel technologies, such as memristors, nanotube, and graphene transistors, are under research as alternatives. Among these technologies, memristor is a promising candidate due to its great scalability, high integration density and near-zero standby power. However, memristor-based logic circuits are facing robustness challenges mainly due to improper values of design parameters (e.g., OFF/ON ratio, control voltages). Moreover, process variation, sneak path currents and parasitic resistance of nanowires also impact the robustness. To realize a robust design, this paper formulates proper constraints for design parameters to guarantee correct functionality of logic gates (e.g., AND). Our proposal is verified with SPICE simulations while taking both device variation and parasitic effects into account. It is observed that the errors due to analytical parameter constraints are typically within 4.5% as compared to simulations.
Original languageEnglish
Title of host publication2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
EditorsM. Dietrich, O. Novak
Place of PublicationPiscataway
PublisherIEEE
Pages158-163
Number of pages6
ISBN (Electronic)978-1-5386-0472-4
ISBN (Print)978-1-5386-0473-1
DOIs
Publication statusPublished - 2017
Event2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Dresden, Germany
Duration: 19 Apr 201721 Apr 2017

Conference

Conference2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
Abbreviated titleDDECS 2017
CountryGermany
CityDresden
Period19/04/1721/04/17

    Research areas

  • Memristors, Logic gates, Switches, Biological system modeling, Resistance, Nanowires, Threshold voltage

ID: 32863202