Abstract
As today's CMOS technology is scaling down to its physical limits, it suffers from major challenges such as increased leakage power and reduced reliability. Novel technologies, such as memristors, nanotube, and graphene transistors, are under research as alternatives. Among these technologies, memristor is a promising candidate due to its great scalability, high integration density and near-zero standby power. However, memristor-based logic circuits are facing robustness challenges mainly due to improper values of design parameters (e.g., OFF/ON ratio, control voltages). Moreover, process variation, sneak path currents and parasitic resistance of nanowires also impact the robustness. To realize a robust design, this paper formulates proper constraints for design parameters to guarantee correct functionality of logic gates (e.g., AND). Our proposal is verified with SPICE simulations while taking both device variation and parasitic effects into account. It is observed that the errors due to analytical parameter constraints are typically within 4.5% as compared to simulations.
Original language | English |
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Title of host publication | 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) |
Editors | M. Dietrich, O. Novak |
Place of Publication | Piscataway |
Publisher | IEEE |
Pages | 158-163 |
Number of pages | 6 |
ISBN (Electronic) | 978-1-5386-0472-4 |
ISBN (Print) | 978-1-5386-0473-1 |
DOIs | |
Publication status | Published - 2017 |
Event | 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Dresden, Germany Duration: 19 Apr 2017 → 21 Apr 2017 |
Conference
Conference | 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) |
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Abbreviated title | DDECS 2017 |
Country/Territory | Germany |
City | Dresden |
Period | 19/04/17 → 21/04/17 |
Keywords
- Memristors
- Logic gates
- Switches
- Biological system modeling
- Resistance
- Nanowires
- Threshold voltage