Optimizing Memory BIST Address Generator Implementations

AJ van de Goor; H Kukner; S Hamdioui

doi:10.1109/DTIS.2011.5941430

Optimizing Memory BIST Address Generator Implementations

AJ van de Goor, H Kukner, S Hamdioui

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

10 Citations (Scopus)

Original language	English
Title of host publication	Proceedings 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era
Editors	S Bernard, C Efstathiou
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE Society
Pages	1-6
Number of pages	6
ISBN (Print)	978-1-61284-899-0
DOIs	https://doi.org/10.1109/DTIS.2011.5941430
Publication status	Published - 2011
Event	DTIS 2011, Athens, Greece - Piscataway, NJ, USA Duration: 6 Apr 2011 → 8 Apr 2011

Publication series

Name
Publisher	IEEE

Conference

Conference	DTIS 2011, Athens, Greece
Period	6/04/11 → 8/04/11

Keywords

Conf.proc. > 3 pag

Access to Document

10.1109/DTIS.2011.5941430

Cite this

@inproceedings{f6f199d915f346c3986a90f4da75d352,

title = "Optimizing Memory BIST Address Generator Implementations",

keywords = "Conf.proc. > 3 pag",

author = "{van de Goor}, AJ and H Kukner and S Hamdioui",

year = "2011",

doi = "10.1109/DTIS.2011.5941430",

language = "English",

isbn = "978-1-61284-899-0",

publisher = "IEEE Society",

pages = "1--6",

editor = "S Bernard and C Efstathiou",

booktitle = "Proceedings 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era",

note = "DTIS 2011, Athens, Greece ; Conference date: 06-04-2011 Through 08-04-2011",

}

van de Goor, AJ, Kukner, H & Hamdioui, S 2011, Optimizing Memory BIST Address Generator Implementations. in S Bernard & C Efstathiou (eds), Proceedings 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era. IEEE Society, Piscataway, NJ, USA, pp. 1-6, DTIS 2011, Athens, Greece, 6/04/11. https://doi.org/10.1109/DTIS.2011.5941430

Optimizing Memory BIST Address Generator Implementations. / van de Goor, AJ; Kukner, H; Hamdioui, S.
Proceedings 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era. ed. / S Bernard; C Efstathiou. Piscataway, NJ, USA: IEEE Society, 2011. p. 1-6.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Optimizing Memory BIST Address Generator Implementations

AU - van de Goor, AJ

AU - Kukner, H

AU - Hamdioui, S

PY - 2011

Y1 - 2011

KW - Conf.proc. > 3 pag

U2 - 10.1109/DTIS.2011.5941430

DO - 10.1109/DTIS.2011.5941430

M3 - Conference contribution

SN - 978-1-61284-899-0

SP - 1

EP - 6

BT - Proceedings 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era

A2 - Bernard, S

A2 - Efstathiou, C

PB - IEEE Society

CY - Piscataway, NJ, USA

T2 - DTIS 2011, Athens, Greece

Y2 - 6 April 2011 through 8 April 2011

ER -