Optimizing test length for soft faults in DRAM devices

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

6 Citations (Scopus)
Original languageUndefined/Unknown
Title of host publication25th IEEE VLSI Test Symposium
Editors s.n.
Place of PublicationPiscataway
PublisherIEEE Society
Pages59-66
Number of pages8
ISBN (Print)0-7695-2812-0
Publication statusPublished - 2007
EventIEEE VTS'07 - Piscataway
Duration: 6 May 200710 May 2007

Publication series

Name
PublisherIEEE

Conference

ConferenceIEEE VTS'07
Period6/05/0710/05/07

Keywords

  • conference contrib. refereed
  • Conf.proc. > 3 pag

Cite this