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Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM. / Kraak, Daniël; Taouil, Mottagiallah; Agbo, Innocent; Hamdioui, Said; Weckx, Pieter; Cosemans, Stefan; Catthoor, Francky.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 6, 8678671, 01.06.2019, p. 1308-1321.

Research output: Contribution to journalArticleScientificpeer-review

Harvard

Kraak, D, Taouil, M, Agbo, I, Hamdioui, S, Weckx, P, Cosemans, S & Catthoor, F 2019, 'Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 6, 8678671, pp. 1308-1321. https://doi.org/10.1109/TVLSI.2019.2902881

APA

Kraak, D., Taouil, M., Agbo, I., Hamdioui, S., Weckx, P., Cosemans, S., & Catthoor, F. (2019). Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(6), 1308-1321. [8678671]. https://doi.org/10.1109/TVLSI.2019.2902881

Vancouver

Kraak D, Taouil M, Agbo I, Hamdioui S, Weckx P, Cosemans S et al. Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2019 Jun 1;27(6):1308-1321. 8678671. https://doi.org/10.1109/TVLSI.2019.2902881

Author

Kraak, Daniël ; Taouil, Mottagiallah ; Agbo, Innocent ; Hamdioui, Said ; Weckx, Pieter ; Cosemans, Stefan ; Catthoor, Francky. / Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2019 ; Vol. 27, No. 6. pp. 1308-1321.

BibTeX

@article{3e310e2d4d4c4db992eab870f163b3a5,
title = "Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM",
abstract = "Designers typically add design margins to compensate for chip aging. However, this leads to yield loss (in case of overestimation) or low reliability (in case of underestimation). This paper analyzes the impact of aging on a complete high-performance industrial 14-nm FinFET SRAM. It investigates the impact on the memory’s parametric (i.e., its delay) and functional (i.e., correct functionality) metrics. Moreover, it examines which components are the main contributors to the degradation of the memory’s reliability and how it is impacted by workload and environmental conditions, i.e., temperature and voltage fluctuations. This paper not only investigates the impact of the memory’s components individually, which is typically the case in prior work, but it also studies the contribution of components’ interaction to the overall memory aging. The results show that the timing circuit, address decoder, and the output latches and buffers are the main contributors to the memory’s parametric degradation, while the cell, sense amplifier, and address decoder are the main contributors to its functional degradation. Moreover, the results show that it is crucial to consider the impact of the interaction of components on the aging; individual analysis leads to overly pessimistic results and even wrong conclusions in certain cases.",
keywords = "Aging, bias temperature instability (BTI), FinFET, reliability, SRAM",
author = "Dani{\"e}l Kraak and Mottagiallah Taouil and Innocent Agbo and Said Hamdioui and Pieter Weckx and Stefan Cosemans and Francky Catthoor",
year = "2019",
month = "6",
day = "1",
doi = "10.1109/TVLSI.2019.2902881",
language = "English",
volume = "27",
pages = "1308--1321",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "6",

}

RIS

TY - JOUR

T1 - Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM

AU - Kraak, Daniël

AU - Taouil, Mottagiallah

AU - Agbo, Innocent

AU - Hamdioui, Said

AU - Weckx, Pieter

AU - Cosemans, Stefan

AU - Catthoor, Francky

PY - 2019/6/1

Y1 - 2019/6/1

N2 - Designers typically add design margins to compensate for chip aging. However, this leads to yield loss (in case of overestimation) or low reliability (in case of underestimation). This paper analyzes the impact of aging on a complete high-performance industrial 14-nm FinFET SRAM. It investigates the impact on the memory’s parametric (i.e., its delay) and functional (i.e., correct functionality) metrics. Moreover, it examines which components are the main contributors to the degradation of the memory’s reliability and how it is impacted by workload and environmental conditions, i.e., temperature and voltage fluctuations. This paper not only investigates the impact of the memory’s components individually, which is typically the case in prior work, but it also studies the contribution of components’ interaction to the overall memory aging. The results show that the timing circuit, address decoder, and the output latches and buffers are the main contributors to the memory’s parametric degradation, while the cell, sense amplifier, and address decoder are the main contributors to its functional degradation. Moreover, the results show that it is crucial to consider the impact of the interaction of components on the aging; individual analysis leads to overly pessimistic results and even wrong conclusions in certain cases.

AB - Designers typically add design margins to compensate for chip aging. However, this leads to yield loss (in case of overestimation) or low reliability (in case of underestimation). This paper analyzes the impact of aging on a complete high-performance industrial 14-nm FinFET SRAM. It investigates the impact on the memory’s parametric (i.e., its delay) and functional (i.e., correct functionality) metrics. Moreover, it examines which components are the main contributors to the degradation of the memory’s reliability and how it is impacted by workload and environmental conditions, i.e., temperature and voltage fluctuations. This paper not only investigates the impact of the memory’s components individually, which is typically the case in prior work, but it also studies the contribution of components’ interaction to the overall memory aging. The results show that the timing circuit, address decoder, and the output latches and buffers are the main contributors to the memory’s parametric degradation, while the cell, sense amplifier, and address decoder are the main contributors to its functional degradation. Moreover, the results show that it is crucial to consider the impact of the interaction of components on the aging; individual analysis leads to overly pessimistic results and even wrong conclusions in certain cases.

KW - Aging

KW - bias temperature instability (BTI)

KW - FinFET

KW - reliability

KW - SRAM

UR - http://www.scopus.com/inward/record.url?scp=85066394699&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2019.2902881

DO - 10.1109/TVLSI.2019.2902881

M3 - Article

VL - 27

SP - 1308

EP - 1321

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

T2 - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 6

M1 - 8678671

ER -

ID: 54216959