The STT-MRAM manufacturing process involves not only traditional CMOS process steps, but also the integration of magnetic tunnel junction (MTJ) devices, the data-storing elements. This paper demonstrates a paradigm shift in fault modeling for STT-MRAMs by performing defect modeling and fault analysis for MTJ pinhole defects which are seen as a key type of STT-MRAM manufacturing defects. A Verilog-A compact model for defect-free MTJ devices is built and calibrated with electrical measurements on actual MTJ wafers. MTJs with a pinhole defect are extensively characterized, both during manufacturing test (t=0) and in the field (t>0), and the data is used to extend our defect-free MTJ compact model to include parameterized pinhole defects. The model is then used to perform single-cell static fault analysis and this shows not only what kind of faults can occur in an STT-MRAM, but also that the conventional fault modeling approach based on linear resistors cannot catch such behavior.
Original languageEnglish
Title of host publication2019 IEEE European Test Symposium (ETS)
Subtitle of host publicationProceedings
Place of PublicationDanvers
Number of pages6
ISBN (Electronic)978-1-7281-1173-5
ISBN (Print) 978-1-7281-1174-2
Publication statusPublished - 2019
Event24th IEEE European Test Symposium 2019 - Baden-Baden, Germany
Duration: 27 May 201931 May 2019
Conference number: 24th


Conference24th IEEE European Test Symposium 2019
Abbreviated titleETS
Internet address

ID: 57081735