TY - JOUR
T1 - Pixel Optimizations and Digital Calibration Methods of a CMOS Image Sensor Targeting High Linearity
AU - Wang, Fei
AU - Theuwissen, Albert J.P.
PY - 2019
Y1 - 2019
N2 - In this paper, different methodologies are employed to improve the linearity performance of a prototype CMOS image sensor (CIS). First, several pixel structures, including a novel pixel design based on a capacitive trans-impedance amplifier (CTIA), are proposed to achieve a higher pixel-level linearity. Furthermore, three types of digital linearity calibration methods are explored. A prototype image sensor designed in 0.18-μm, 1-poly, and 4-metal CIS technology with a pixel array of 128 × 160 is used to verify these linearity improvement techniques. The measurement results show that the proposed CTIA pixel has the best linearity result out of all pixel structures. Meanwhile, the proposed calibration methods further improved the linearity of the CIS without changing the pixel structure. The pixel mode method achieves the most significant improvement on the linearity. One type of 4T pixel attains a nonlinearity of 0.028% with pixel mode calibration, which is two times better than the state of the art. Voltage mode (VM) and current mode (CM) calibration methods get rid of the limitation on the illumination condition during calibration operation; especially, CM calibration can further suppress the nonlinearity caused by the integration capacitor C FD on the floating diffusion node, which is remnant in VM.
AB - In this paper, different methodologies are employed to improve the linearity performance of a prototype CMOS image sensor (CIS). First, several pixel structures, including a novel pixel design based on a capacitive trans-impedance amplifier (CTIA), are proposed to achieve a higher pixel-level linearity. Furthermore, three types of digital linearity calibration methods are explored. A prototype image sensor designed in 0.18-μm, 1-poly, and 4-metal CIS technology with a pixel array of 128 × 160 is used to verify these linearity improvement techniques. The measurement results show that the proposed CTIA pixel has the best linearity result out of all pixel structures. Meanwhile, the proposed calibration methods further improved the linearity of the CIS without changing the pixel structure. The pixel mode method achieves the most significant improvement on the linearity. One type of 4T pixel attains a nonlinearity of 0.028% with pixel mode calibration, which is two times better than the state of the art. Voltage mode (VM) and current mode (CM) calibration methods get rid of the limitation on the illumination condition during calibration operation; especially, CM calibration can further suppress the nonlinearity caused by the integration capacitor C FD on the floating diffusion node, which is remnant in VM.
KW - CMOS image sensor
KW - pixel
KW - linearity
KW - CTIA
KW - calibration
UR - http://www.scopus.com/inward/record.url?scp=85055024747&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2018.2872627
DO - 10.1109/TCSI.2018.2872627
M3 - Article
AN - SCOPUS:85055024747
SN - 1549-8328
VL - 66
SP - 930
EP - 940
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 3
M1 - 8490722
ER -