Post-bond interconnect test and diagnosis for 3-D memory stacked on logic

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11 Citations (Scopus)

Original language	English
Pages (from-to)	1860-1872
Number of pages	13
Journal	IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems
Volume	34
Issue number	11
DOIs	https://doi.org/10.1109/TCAD.2015.2432142
Publication status	Published - 2015

Harvest
Date of publication 12-5-2015

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title = "Post-bond interconnect test and diagnosis for 3-D memory stacked on logic",

author = "M Taouil and S Hamdioui",

note = "Harvest Date of publication 12-5-2015",

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journal = "IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

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T1 - Post-bond interconnect test and diagnosis for 3-D memory stacked on logic

AU - Taouil, M

AU - Hamdioui, S

N1 - Harvest Date of publication 12-5-2015

PY - 2015

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U2 - 10.1109/TCAD.2015.2432142

DO - 10.1109/TCAD.2015.2432142

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VL - 34

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EP - 1872

JO - IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems

IS - 11

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