Power and Area Efficient Column-Parallel ADC Architectures for CMOS Image Sensors

MF Snoeij; AJP Theuwissen; JH Huijsing; KAA Makinwa

doi:doi:10.1109/ICSENS.2007.4388451

Power and Area Efficient Column-Parallel ADC Architectures for CMOS Image Sensors

MF Snoeij, AJP Theuwissen, JH Huijsing, KAA Makinwa

Electronic Instrumentation

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific

9 Citations (Scopus)

Abstract

The ever-increasing resolution of CMOS imagers has had a profound impact on their analog readout electronics, and, in particular, on their ADC architecture. This paper gives an overview of the development of column-parallel ADCs that enable the high-speed and power-efficient readout of high-resolution CMOS imagers. In particular, the recently proposed multiple-ramp single-slope (MRSS) ADC will be discussed.

Original language	Undefined/Unknown
Title of host publication	Proceedings IEEE Sensors 2007
Editors	s.n.
Place of Publication	Atlanta
Publisher	IEEE Society
Pages	523-526
Number of pages	4
ISBN (Print)	978-1-4244-1262-4
DOIs	https://doi.org/doi:10.1109/ICSENS.2007.4388451
Publication status	Published - 2007
Event	IEEE Sensors 2007: 6th IEEE Conference on Sensors - Atlanta, GA, United States Duration: 28 Oct 2007 → 31 Oct 2007

Conference

Conference	IEEE Sensors 2007
Country/Territory	United States
City	Atlanta, GA
Period	28/10/07 → 31/10/07

Keywords

academic journal papers
Conf.proc. > 3 pag

Access to Document

doi:10.1109/ICSENS.2007.4388451

Cite this

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title = "Power and Area Efficient Column-Parallel ADC Architectures for CMOS Image Sensors",

abstract = "The ever-increasing resolution of CMOS imagers has had a profound impact on their analog readout electronics, and, in particular, on their ADC architecture. This paper gives an overview of the development of column-parallel ADCs that enable the high-speed and power-efficient readout of high-resolution CMOS imagers. In particular, the recently proposed multiple-ramp single-slope (MRSS) ADC will be discussed.",

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T1 - Power and Area Efficient Column-Parallel ADC Architectures for CMOS Image Sensors

AU - Snoeij, MF

AU - Theuwissen, AJP

AU - Huijsing, JH

AU - Makinwa, KAA

PY - 2007

Y1 - 2007

N2 - The ever-increasing resolution of CMOS imagers has had a profound impact on their analog readout electronics, and, in particular, on their ADC architecture. This paper gives an overview of the development of column-parallel ADCs that enable the high-speed and power-efficient readout of high-resolution CMOS imagers. In particular, the recently proposed multiple-ramp single-slope (MRSS) ADC will be discussed.

AB - The ever-increasing resolution of CMOS imagers has had a profound impact on their analog readout electronics, and, in particular, on their ADC architecture. This paper gives an overview of the development of column-parallel ADCs that enable the high-speed and power-efficient readout of high-resolution CMOS imagers. In particular, the recently proposed multiple-ramp single-slope (MRSS) ADC will be discussed.

KW - academic journal papers

KW - Conf.proc. > 3 pag

U2 - doi:10.1109/ICSENS.2007.4388451

DO - doi:10.1109/ICSENS.2007.4388451

M3 - Conference contribution

SN - 978-1-4244-1262-4

SP - 523

EP - 526

BT - Proceedings IEEE Sensors 2007

A2 - s.n., null

PB - IEEE Society

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