DOI

Nowadays, typical (memory) designers add design margins to compensate for uncertainties, however, this may be overestimated leading to yield loss, or underestimated leading to reduced reliability designs. Accurate quantification of all uncertainties is therefore critical to provide high quality and optimal designs. These uncertainties are caused by zero-time variability (due to process variability), and by run-time variability(due to environmental variabilities such as voltage and temperature, or due to temporal variability such as aging). This paper uses an accurate methodology to predict the impact of both zero-and run-time variability on the offset voltage of sense amplifiers while considering different workloads and PVT variations for a pre-defined failure rate. The results show a marginal impact of environmental run-time variability on the offset specification when considering zero-time variability only, while this becomes significant (up to 2X) when incorporating aging run-time variability. The results can be used to quantify whether the required offset voltage is met or not for the targeted lifetime, hence, enable the designer to take appropriate measures for an efficient and optimized design, depending on the targeted application lifetime.
Original languageEnglish
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2016)
EditorsBaris Taskin, Prasun Ghosal
Place of PublicationLos Alamitos, CA
PublisherIEEE
Pages725-730
Number of pages6
ISBN (Electronic)978-1-4673-9039-2
ISBN (Print)978-1-4673-9038-5
DOIs
Publication statusPublished - 2016

    Research areas

  • SRAM sense amplifier, Offset voltage, zero-time variability, run-time variability

ID: 10408139