Reconfigurable multiple operation array

S Vassiliadis; H Calderón

doi:doi:10.1007/11512622_4

Reconfigurable multiple operation array

S Vassiliadis, H Calderón

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

3 Citations (Scopus)

Abstract

In this paper, we investigate the collapsing of eight multi-operand addition related operations into a single and common (3:2) counter array. We consider for this unit multiplication in integer and fractional representations, the Sum of Absolute Differences (SAD) in unsigned, signed magnitude and two¿s complement notation. Furthermore, the unit also incorporates a Multiply-Accumulation unit (MAC) for two¿s complement notation. The proposed multiple operation unit was constructed around 10 element arrays that can be reduced using well known counter techniques, which are feed with the necessary data to perform the proposed eight operations. It is estimated that 6/8 of the basic (3:2) counter array is shared by the operations. The obtained results of the presented unit indicates that is capable of processing a 4x4 SAD macro-block in 36.35 ns and takes 30.43 ns to process the rest of the operations using a VIRTEX II PRO xc2vp100-7ff1696 FPGA device.

Original language	Undefined/Unknown
Title of host publication	Proceedings of the 5th international workshop on computer systems: architectures, modelling, and simulation (SAMOS 2005)
Editors	TD Hämäläinen, AD Pimentel, J Takala, S Vassiliadis
Place of Publication	Berlin
Publisher	Springer
Pages	22-31
Number of pages	10
ISBN (Print)	3-540-26969-X
DOIs	https://doi.org/doi:10.1007/11512622_4
Publication status	Published - 2005
Event	5th international workshop on computer systems: architectures, modelling, and simulation (SAMOS 2005), Samos, Greece - Berlin Duration: 18 Jul 2005 → 20 Jul 2005

Publication series

Name
Publisher	Springer

Name	Lecture Notes in Computer Science
Volume	3553
ISSN (Print)	0302-9743

Conference

Conference	5th international workshop on computer systems: architectures, modelling, and simulation (SAMOS 2005), Samos, Greece
Period	18/07/05 → 20/07/05

Keywords

conference contrib. refereed
ZX CWTS JFIS < 1.00

Access to Document

doi:10.1007/11512622_4

Cite this

Vassiliadis, S., & Calderón, H. (2005). Reconfigurable multiple operation array. In TD. Hämäläinen, AD. Pimentel, J. Takala, & S. Vassiliadis (Eds.), Proceedings of the 5th international workshop on computer systems: architectures, modelling, and simulation (SAMOS 2005) (pp. 22-31). (Lecture Notes in Computer Science; Vol. 3553). Springer. https://doi.org/doi:10.1007/11512622_4

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abstract = "In this paper, we investigate the collapsing of eight multi-operand addition related operations into a single and common (3:2) counter array. We consider for this unit multiplication in integer and fractional representations, the Sum of Absolute Differences (SAD) in unsigned, signed magnitude and two¿s complement notation. Furthermore, the unit also incorporates a Multiply-Accumulation unit (MAC) for two¿s complement notation. The proposed multiple operation unit was constructed around 10 element arrays that can be reduced using well known counter techniques, which are feed with the necessary data to perform the proposed eight operations. It is estimated that 6/8 of the basic (3:2) counter array is shared by the operations. The obtained results of the presented unit indicates that is capable of processing a 4x4 SAD macro-block in 36.35 ns and takes 30.43 ns to process the rest of the operations using a VIRTEX II PRO xc2vp100-7ff1696 FPGA device.",

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author = "S Vassiliadis and H Calder{\'o}n",

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Vassiliadis, S & Calderón, H 2005, Reconfigurable multiple operation array. in TD Hämäläinen, AD Pimentel, J Takala & S Vassiliadis (eds), Proceedings of the 5th international workshop on computer systems: architectures, modelling, and simulation (SAMOS 2005). Lecture Notes in Computer Science, vol. 3553, Springer, Berlin, pp. 22-31, 5th international workshop on computer systems: architectures, modelling, and simulation (SAMOS 2005), Samos, Greece, 18/07/05. https://doi.org/doi:10.1007/11512622_4

Reconfigurable multiple operation array. / Vassiliadis, S; Calderón, H.
Proceedings of the 5th international workshop on computer systems: architectures, modelling, and simulation (SAMOS 2005). ed. / TD Hämäläinen; AD Pimentel; J Takala; S Vassiliadis. Berlin: Springer, 2005. p. 22-31 (Lecture Notes in Computer Science; Vol. 3553).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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AB - In this paper, we investigate the collapsing of eight multi-operand addition related operations into a single and common (3:2) counter array. We consider for this unit multiplication in integer and fractional representations, the Sum of Absolute Differences (SAD) in unsigned, signed magnitude and two¿s complement notation. Furthermore, the unit also incorporates a Multiply-Accumulation unit (MAC) for two¿s complement notation. The proposed multiple operation unit was constructed around 10 element arrays that can be reduced using well known counter techniques, which are feed with the necessary data to perform the proposed eight operations. It is estimated that 6/8 of the basic (3:2) counter array is shared by the operations. The obtained results of the presented unit indicates that is capable of processing a 4x4 SAD macro-block in 36.35 ns and takes 30.43 ns to process the rest of the operations using a VIRTEX II PRO xc2vp100-7ff1696 FPGA device.

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