Documents

  • 10300375

    Accepted author manuscript, 559 KB, PDF-document

DOI

Emerging technologies such as RRAMs are attracting significant attention, due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures (such as process variation due to their nano-scale structure) have gained considerable importance for having acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circuit and system level. In this paper we have first reviewed the RRAM variability phenomenon and the variation tolerant techniques at the circuit level. Then we have analyzed the impact of variability on memory reliability and have proposed a variation-monitoring circuit that discerns the reliable memory cells affected by process variability.
Original languageEnglish
Title of host publication26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages141-146
Number of pages6
ISBN (Electronic)978-1-5090-0733-2
DOIs
Publication statusPublished - 2016
Event26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016 - Bremen, Germany
Duration: 21 Sep 201623 Sep 2016

Workshop

Workshop26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016
CountryGermany
CityBremen
Period21/09/1623/09/16
OtherPATMOS 2016 is co-located with VARI 2016

    Research areas

  • RRAM, Reliability, Process Variability, Mitagation, Emerging Memory, Resistive Memory

ID: 10300375