RRAM Variability and its Mitigation Schemes

Peyman Pouyan; Esteve Amat; Said Hamdioui; Antonio Rubio

doi:10.1109/PATMOS.2016.7833679

RRAM Variability and its Mitigation Schemes

Peyman Pouyan, Esteve Amat, Said Hamdioui, Antonio Rubio

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

17 Citations (Scopus)

137 Downloads (Pure)

Abstract

Emerging technologies such as RRAMs are attracting significant attention, due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures (such as process variation due to their nano-scale structure) have gained considerable importance for having acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circuit and system level. In this paper we have first reviewed the RRAM variability phenomenon and the variation tolerant techniques at the circuit level. Then we have analyzed the impact of variability on memory reliability and have proposed a variation-monitoring circuit that discerns the reliable memory cells affected by process variability.

Original language	English
Title of host publication	26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	141-146
Number of pages	6
ISBN (Electronic)	978-1-5090-0733-2
DOIs	https://doi.org/10.1109/PATMOS.2016.7833679
Publication status	Published - 2016
Event	26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016 - Bremen, Germany Duration: 21 Sept 2016 → 23 Sept 2016

Workshop

Workshop	26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016
Country/Territory	Germany
City	Bremen
Period	21/09/16 → 23/09/16
Other	PATMOS 2016 is co-located with VARI 2016

Keywords

RRAM
Reliability
Process Variability
Mitagation
Emerging Memory
Resistive Memory

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10.1109/PATMOS.2016.7833679

10300375Accepted author manuscript, 560 KB

Cite this

@inproceedings{dd499c045ee848849b5469f7b4f6e756,

title = "RRAM Variability and its Mitigation Schemes",

abstract = "Emerging technologies such as RRAMs are attracting significant attention, due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures (such as process variation due to their nano-scale structure) have gained considerable importance for having acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circuit and system level. In this paper we have first reviewed the RRAM variability phenomenon and the variation tolerant techniques at the circuit level. Then we have analyzed the impact of variability on memory reliability and have proposed a variation-monitoring circuit that discerns the reliable memory cells affected by process variability.",

keywords = "RRAM, Reliability, Process Variability, Mitagation, Emerging Memory, Resistive Memory",

author = "Peyman Pouyan and Esteve Amat and Said Hamdioui and Antonio Rubio",

year = "2016",

doi = "10.1109/PATMOS.2016.7833679",

language = "English",

pages = "141--146",

booktitle = "26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016",

publisher = "IEEE",

address = "United States",

note = "26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016 ; Conference date: 21-09-2016 Through 23-09-2016",

}

Pouyan, P, Amat, E, Hamdioui, S & Rubio, A 2016, RRAM Variability and its Mitigation Schemes. in 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016. IEEE, Piscataway, NJ, pp. 141-146, 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, 21/09/16. https://doi.org/10.1109/PATMOS.2016.7833679

TY - GEN

T1 - RRAM Variability and its Mitigation Schemes

AU - Pouyan, Peyman

AU - Amat, Esteve

AU - Hamdioui, Said

AU - Rubio, Antonio

PY - 2016

Y1 - 2016

N2 - Emerging technologies such as RRAMs are attracting significant attention, due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures (such as process variation due to their nano-scale structure) have gained considerable importance for having acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circuit and system level. In this paper we have first reviewed the RRAM variability phenomenon and the variation tolerant techniques at the circuit level. Then we have analyzed the impact of variability on memory reliability and have proposed a variation-monitoring circuit that discerns the reliable memory cells affected by process variability.

AB - Emerging technologies such as RRAMs are attracting significant attention, due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures (such as process variation due to their nano-scale structure) have gained considerable importance for having acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circuit and system level. In this paper we have first reviewed the RRAM variability phenomenon and the variation tolerant techniques at the circuit level. Then we have analyzed the impact of variability on memory reliability and have proposed a variation-monitoring circuit that discerns the reliable memory cells affected by process variability.

KW - RRAM

KW - Reliability

KW - Process Variability

KW - Mitagation

KW - Emerging Memory

KW - Resistive Memory

UR - http://resolver.tudelft.nl/uuid:dd499c04-5ee8-4884-9b54-69f7b4f6e756

U2 - 10.1109/PATMOS.2016.7833679

DO - 10.1109/PATMOS.2016.7833679

M3 - Conference contribution

SP - 141

EP - 146

BT - 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016

PB - IEEE

CY - Piscataway, NJ

T2 - 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016

Y2 - 21 September 2016 through 23 September 2016

ER -

RRAM Variability and its Mitigation Schemes

Abstract

Workshop

Keywords

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