Scaling Aspects of Silicon Spin Qubits

To harness the potential of quantum mechanics for quantum computation applications, one of the main challenges is to scale up the number of qubits. The work presented in this dissertation is concerned with several aspects that are relevant in the quest of scaling up quantum computing systems based on spin qubits in silicon. Few-qubit experiments are maturing quickly, but simultaneously the lacuna between them and large-scale quantum computers is filled with a combination of science and engineering challenges. The challenges that are addressed in this dissertation are reliable and reproducible sample fabrication, qubit resilience to temperature, spatial correlations in the noise affecting the qubits, and co-integration of qubits with classical control electronics.

I start with describing the development of an integration scheme for silicon spin qubits in an academic cleanroom environment, as several research groups have demonstrated over the last years. This has allowed them to successfully fabricate and operate silicon spin qubit devices. The development of such a scheme is crucial for the fabrication of proof-of-principle devices, and the testing of several design variations for more and more complex qubit devices, before transferring the optimal designs to industrial foundries that are generally less flexible. Moreover, it is essential for performing paramount few-qubit experiments in the near term. The developed scheme has been successfully implemented in the next chapter of this thesis.

In the first experiment, we investigate the effect of temperature on the spin lifetime, as a first step towards higher temperature operation of silicon spin qubits. Spin qubit operation at elevated temperatures will be required to allow for co-integration of qubits with classical control electronics on a single chip, since the heat load associated with this electronics will be too much to deal with at the current qubit operation temperature of ∼10 mK. At a temperature of ∼1-4 K, significantly more cooling power is available (see for example CERN's Large Hadron Collider). Such co-integration would alleviate the interconnect bottleneck and facilitate the implementation of local control in large-scale devices. We find only a modest temperature dependence and measure a spin relaxation time of 2.8 ms at 1.1 K (still much longer than the record spin dephasing time measured in such a system). In addition, we present a theoretical model and use it in combination with our experimentally obtained parameters to demonstrate that the spin relaxation time can be enhanced by low magnetic field operation and by employing high-valley-splitting devices. Together with more recent work, this experiment demonstrates no fundamental limitations to prevent high-temperature operation of silicon spin qubits. Simultaneously, bringing classical control electronics to lower temperatures also is an active research area.

The second experiment uses maximally entangled Bell states of two qubits to study spatial correlations in the noise acting on those two qubits. Spatial correlations in qubit errors hinder quantum error corrections schemes that will be required for fault-tolerant large-scale quantum computers, as these schemes are commonly derived under the assumption of negligible correlations in qubit errors. Therefore, it is important to know to what extent the noise causing these errors is correlated. We find only modest spatial correlations in the noise and gain insight in their origin. The data is in accordance with decoherence being dominated by a combination of nuclear spins and multiple distant charge fluctuators coupling asymmetrically to the two qubits. We recommend to perform similar experiments in isotopically purified silicon to eliminate the effect of nuclear spins and in isolation study spatial correlations in charge noise. Furthermore, our insights show how correlations can be either maximized or minimized through qubit device design. For these reasons, the prospects for the development and implementation of quantum error correction schemes in fault-tolerant large-scale quantum computers are promising.

Finally, after having studied several aspects that are relevant to determine the suitability of silicon spin qubits for large-scale quantum computation in the preceding experiments, we propose a concrete physical implementation of co-integrated spin qubits with classical control electronics in a sparse spin qubit array. While the community usually claims compatibility of silicon spin qubits with conventional CMOS fabrication, existing proposals make assumptions that remain to be validated. Implementing quantum error correction protocols in a sparse array has been studied, but the description of a physical implementation was largely missing. The sparseness of the array allows for integration of local control electronics, as shown to be promising earlier in this thesis. Specifically, we propose to implement sample-and-hold circuits alongside the qubit circuitry that would allow to offset inhomogeneity in the qubit array. This enables individual local control and shared global control, resulting in an efficient line scaling. The scalable unit cell design fits 2²⁰ (≈10⁶) qubits in ∼150 mm².
We assess the feasibility of the proposed scheme, as well as its physical implementation and the associated footprint, line scaling and interconnect density.